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1. general description the lpc2917/2919/01 combine an arm968e-s cpu core with two integrated tcm blocks operating at frequencies of up to 125 mhz, can and lin, 56 kb sram, up to 768 kb flash memory, external memory interface, two 10-bit adcs, and multiple serial and parallel interfaces in a single chip target ed at consumer, industrial, medical, and communication markets. to optimize system power consumption, the lpc2917/2919/01 has a very flexible clock generation unit (c gu) that provides dynamic clock gating and scaling. 2. features ? arm968e-s processor running at frequencies of up to 125 mhz maximum. ? multi-layer ahb system bus at 12 5 mhz with three separate layers. ? on-chip memory: ? two tightly coupled memories (tcm), 16 kb instruction tcm (itcm), 16 kb data tcm (dtcm). ? two separate internal static ram (s ram) instances; 32 kb sram and 16 kb sram. ? 8 kb etb sram also available for code execution and data. ? up to 768 kb high-speed flash-program memory. ? 16 kb true eeprom, byte-erasable and programmable. ? dual-master, eight-channel gpdma controller on the ahb multi-layer matrix which can be used with the spi interfaces and the ua rts, as well as for memory-to-memory transfers including the tcm memories. ? external static memory controller (smc) with eight memory banks; up to 32-bit data bus; up to 24-bit address bus. ? serial interfaces: ? two-channel can controller supporting fu llcan and extensive message filtering ? two lin master controllers with full hardware support for lin communication. the lin interface can be configured as uart to provide two additional uart interfaces. ? two 550 uarts with 16-byte tx and rx fifo depths, dma support, and rs485/eia-485 (9 bit) support. ? three full-duplex q-spis with four slave-sele ct lines; 16 bits wide; 8 locations deep; tx fifo and rx fifo. ? two i 2 c-bus interfaces. lpc2917/2919/01 arm9 microcontrolle r with can and lin rev. 03 ? 9 december 2009 product data sheet
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 2 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? other peripherals: ? two 10-bit adcs, 8 channels each, with 3.3 v measurement range and conversion times as low as 2.44 s per channel. each channel provides a compare function to minimize interrupts. ? multiple trigger-start option for all adcs : timer, pwm, other adc, and external signal input. ? four 32-bit timers each containing four capture-and-compare registers linked to i/os. ? four six-channel pwms (pulse-width modulators) with capture and trap functionality. ? two dedicated 32-bit timers to sch edule and synchronize pwm and adc. ? quadrature encoder interfac e that can monitor one external quadrature encoder. ? 32-bit watchdog with timer change protection, running on safe clock. ? up to 108 general-purpose i/o pins with programmable pull-up, pull-down, or bus keeper. ? vectored interrupt controller (vic) with 16 priority levels. ? up to 19 level-sensitive external interr upt pins, including can and lin wake-up features. ? configurable clock-out pin for dr iving external system clocks. ? processor wake-up from power-down via exter nal interrupt pins; can or lin activity. ? flexible reset genera tor unit (rgu) able to control resets of individual modules. ? flexible clock-generation unit (cgu0) able to control clock frequency of individual modules: ? on-chip very low-power ring oscillator; fi xed frequency of 0.4 mhz; always on to provide a safe_clock source for system monitoring. ? on-chip crystal oscillator with a recomm ended operating range from 10 mhz to 25 mhz. pll input range 10 mhz to 25 mhz. ? on-chip pll allows cpu operation up to a maximum cpu rate of 125 mhz. ? generation of up to 11 base clocks. ? seven fractional dividers. ? second cgu (cgu1) with its own pll generates a configurable clock output. ? highly configurable system power management unit (pmu): ? clock control of individual modules. ? allows minimization of system operatin g power consumption in any configuration. ? standard arm test and debug interfac e with real-time in-circuit emulator. ? boundary-scan test supported. ? etm/etb debug functions with 8 kb of dedicated sram also accessible for application code and data storage. ? dual power supply: ? cpu operating voltage: 1.8 v 5%. ? i/o operating voltage: 2.7 v to 3.6 v; inputs tolerant up to 5.5 v. ? 144-pin lqfp package. ? ? 40 c to +85 c ambient operating temperature range.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 3 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version LPC2917FBD144/01 lqfp144 plastic low prof ile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc2919fbd144/01 lqfp144 plastic low prof ile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 table 2. part options type number flash memory sram smc lin 2.0 can package LPC2917FBD144/01 512 kb 56 kb + 2 16 kb tcm 32-bit 2 2 lqfp144 lpc2919fbd144/01 768 kb 56 kb + 2 16 kb tcm 32-bit 2 2 lqfp144
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 4 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 4. block diagram grey-shaded blocks represent peripherals and memory regions accessible by the gpdma. fig 1. lpc2917/2919/01 block diagram 002aad959 arm968e-s dtcm 16 kb itcm 16 kb test/debug interface slave slave slave slave slave slave slave slave external static memory controller gpdma controller gpdma registers embedded flash 512/768 kb 16 kb eeprom embedded sram 32 kb system control timer0/1 mtmr can0/1 global acceptance filter lin0/1 pwm0/1/2/3 3.3 v adc1/2 event router embedded sram 16 kb general purpose i/o ports 0/1/2/3 timer 0/1/2/3 spi0/1/2 rs485 uart0/1 wdt master master slave ahb to apb bridge ahb to dtl bridge vectored interrupt controller ahb to dtl bridge ahb to apb bridge quadrature encoder chip feature id ahb to apb bridge i 2 c0/1 ahb to apb bridge clock generation unit cgu0/1 power management unit reset generation unit lpc2917/01 lpc2919/01 jtag interface 8 kb sram slave slave 1 master 2 slave ahb multi layer matrix
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 5 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 5. pinning information 5.1 pinning 5.2 pin description 5.2.1 general description the lpc2917/2919/01 has up to four ports: two of 32 pins each, one of 28 pins and one of 16 pins. the pin to which each function is assi gned is controlled by the sfsp registers in the scu. the functions combined on each port pin are shown in the pi n description tables in this section. 5.2.2 lqfp144 pin assignment fig 2. pin configuration for sot486-1 (lqfp144) LPC2917FBD144/01 lpc2919fbd144/01 108 37 72 144 109 73 1 36 002aae26 5 table 3. lqfp144 pin assignment pin name pin description default function function 1 function 2 function 3 tdo 1 [1] ieee 1149.1 test data out p2[21]/sdi2/ pcap2[1]/d19 2 [1] gpio 2, pin 21 spi2 sdi pwm2 cap1 extbus d19 p0[24]/txd1/ txdc1/scs2[0] 3 [1] gpio 0, pin 24 uart1 txd can1 txd spi2 scs0 p0[25]/rxd1/ rxdc1/sdo2 4 [1] gpio 0, pin 25 uart1 rxd can1 rxd spi2 sdo p0[26]/txd1/ sdi2 5 [1] gpio 0, pin 26 - uart1 txd spi2 sdi p0[27]/rxd1/ sck2 6 [1] gpio 0, pin 27 - uart1 rxd spi2 sck p0[28]/cap0[0]/ mat0[0] 7 [1] gpio 0, pin 28 - timer0 cap0 timer0 mat0 p0[29]/cap0[1]/ mat0[1] 8 [1] gpio 0, pin 29 - timer0 cap1 timer0 mat1 v dd(io) 9 3.3 v power supply for i/o
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 6 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin p2[22]/sck2/ pcap2[2]/d20 10 [1] gpio 2, pin 22 spi2 sck pwm2 cap2 extbus d20 p2[23]/scs1[0]/ pcap3[0]/d21 11 [1] gpio 2, pin 23 spi1 scs0 pwm3 cap0 extbus d21 p3[6]/scs0[3]/ pmat1[0]/ txdl1 12 [1] gpio 3, pin 6 spi0 scs3 pwm1 mat0 lin1/uart txd p3[7]/scs2[1]/ pmat1[1]/ rxdl1 13 [1] gpio 3, pin 7 spi2 scs1 pwm1 mat1 lin1/uart rxd p0[30]/cap0[2]/ mat0[2] 14 [1] gpio 0, pin 30 - timer0 cap2 timer0 mat2 p0[31]/cap0[3]/ mat0[3] 15 [1] gpio 0, pin 31 - timer0 cap3 timer0 mat3 p2[24]/scs1[1]/ pcap3[1]/d22 16 [1] gpio 2, pin 24 spi1 scs1 pwm3 cap1 extbus d22 p2[25]/scs1[2]/ pcap3[2]/d23 17 [1] gpio 2, pin 25 spi1 scs2 pwm3 cap2 extbus d23 v dd(core) 18 1.8 v power supply for digital core v ss(core) 19 ground for digital core p1[31]/cap0[1]/ mat0[1]/ei5 20 [1] gpio 1, pin 31 timer0 cap1 timer0 mat1 extint5 v ss(io) 21 ground for i/o p1[30]/cap0[0]/ mat0[0]/ei4 22 [1] gpio 1, pin 30 timer0 cap0 timer0 mat0 extint4 p3[8]/scs2[0]/ pmat1[2] 23 [1] gpio 3, pin 8 spi2 scs0 pwm1 mat2 - p3[9]/sdo2/pm at1[3] 24 [1] gpio 3, pin 9 spi2 sdo pwm1 mat3 - p1[29]/cap1[0]/ trap0/ pmat3[5] 25 [1] gpio 1, pin 29 timer1 cap0 pwm trap0 pwm3 mat5 p1[28]/cap1[1]/ trap1/ pmat3[4] 26 [1] gpio 1, pin 28 timer1 cap1, adc1 ext start pwm trap1 pwm3 mat4 p2[26]/cap0[2]/ mat0[2]/ei6 27 [1] gpio 2, pin 26 timer0 cap2 timer0 mat2 extint6 p2[27]/cap0[3]/ mat0[3]/ei7 28 [1] gpio 2, pin 27 timer0 cap3 timer0 mat3 extint7 p1[27]/cap1[2]/ trap2/ pmat3[3] 29 [1] gpio 1, pin 27 timer1 cap2, adc2 ext start pwm trap2 pwm3 mat3 p1[26]/ pmat2[0]/ trap3/ pmat3[2] 30 [1] gpio 1, pin 26 pwm2 mat0 pwm trap3 pwm3 mat2 table 3. lqfp144 pin assignment ?continued pin name pin description default function function 1 function 2 function 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 7 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin v dd(io) 31 3.3 v power supply for i/o p1[25]/ pmat1[0]/ pmat3[1] 32 [1] gpio 1, pin 25 pwm1 mat0 - pwm3 mat1 p1[24]/ pmat0[0]/ pmat3[0] 33 [1] gpio 1, pin 24 pwm0 mat0 - pwm3 mat0 p1[23]/ rxd0/cs5 34 [1] gpio 1, pin 23 uart0 rxd - extbus cs5 p1[22]/txd0/ cs4 35 [1] gpio 1, pin 22 uart0 txd - extbus cs4 tms 36 [1] ieee 1149.1 test mode se lect, pulled up internally tck 37 [1] ieee 1149.1 test clock p1[21]/cap3[3]/ cap1[3]/d7 38 [1] gpio 1, pin 21 timer3 cap3 timer1 cap3, mscss pause extbus d7 p1[20]/cap3[2]/ scs0[1]/d6 39 [1] gpio 1, pin 20 timer3 cap2 spi0 scs1 extbus d6 p1[19]/cap3[1]/ scs0[2]/d5 40 [1] gpio 1, pin 19 timer3 cap1 spi0 scs2 extbus d5 p1[18]/cap3[0]/ sdo0/d4 41 [1] gpio 1, pin 18 timer3 cap0 spi0 sdo extbus d4 p1[17]/cap2[3]/ sdi0/d3 42 [1] gpio 1, pin 17 timer2 cap3 spi0 sdi extbus d3 v ss(io) 43 ground for i/o p1[16]/cap2[2]/ sck0/d2 44 [1] gpio 1, pin 16 timer2 cap2 spi0 sck extbus d2 p2[0]/mat2[0]/ trap3/d8 45 [1] gpio 2, pin 0 timer2 mat0 pwm trap3 extbus d8 p2[1]/mat2[1]/ trap2/d9 46 [1] gpio 2, pin 1 timer2 mat1 pwm trap2 extbus d9 p3[10]/sdi2/ pmat1[4] 47 [1] gpio 3, pin 10 spi2 sdi pwm1 mat4 - p3[11]/sck2/ pmat1[5] 48 [1] gpio 3, pin 11 spi2 sck pwm1 mat5 - p1[15]/cap2[1]/ scs0[0]/d1 49 [1] gpio 1, pin 15 timer2 cap1 spi0 scs0 extbus d1 p1[14]/cap2[0]/ scs0[3]/d0 50 [1] gpio 1, pin 14 timer2 cap0 spi0 scs3 extbus d0 p1[13]/scl1/ ei3/we 51 [1] gpio 1, pin 13 extint3 i2c1 scl extbus we p1[12]/sda1/ ei2/oe 52 [1] gpio 1, pin 12 extint2 i2c1 sda extbus oe v dd(io) 53 3.3 v power supply for i/o p2[2]/mat2[2]/ trap1/d10 54 [1] gpio 2, pin 2 timer2 mat2 pwm trap1 extbus d10 table 3. lqfp144 pin assignment ?continued pin name pin description default function function 1 function 2 function 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 8 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin p2[3]/mat2[3]/ trap0/d11 55 [1] gpio 2, pin 3 timer2 mat3 pwm trap0 extbus d11 p1[11]/sck1/ scl0/cs3 56 [1] gpio 1, pin 11 spi1 sck i2c0 scl extbus cs3 p1[10]/sdi1/ sda0/cs2 57 [1] gpio 1, pin 10 spi1 sdi i2c0 sda extbus cs2 p3[12]/scs1[0]/ ei4 58 [1] gpio 3, pin 12 spi1 scs0 extint4 - v ss(core) 59 ground for digital core v dd(core) 60 1.8 v power supply for digital core p3[13]/sdo1/ ei5/idx0 61 [1] gpio 3, pin 13 spi1 sdo extint5 qei0 idx p2[4]/mat1[0]/ ei0/d12 62 [1] gpio 2, pin 4 timer1 mat0 extint0 extbus d12 p2[5]/mat1[1]/ ei1/d13 63 [1] gpio 2, pin 5 timer1 mat1 extint1 extbus d13 p1[9]/sdo1/ rxdl1/cs1 64 [1] gpio 1, pin 9 spi1 sdo lin1/uart rxd extbus cs1 v ss(io) 65 ground for i/o p1[8]/scs1[0]/ txdl1/cs0 66 [1] gpio 1, pin 8 spi1 scs0 lin1/uart txd extbus cs0 p1[7]/scs1[3]/ rxd1/a7 67 [1] gpio 1, pin 7 spi1 scs3 uart1 rxd extbus a7 p1[6]/scs1[2]/ txd1/a6 68 [1] gpio 1, pin 6 spi1 scs2 uart1 txd extbus a6 p2[6]/mat1[2]/ ei2/d14 69 [1] gpio 2, pin 6 timer1 mat2 extint2 extbus d14 p1[5]/scs1[1]/ pmat3[5]/a5 70 [1] gpio 1, pin 5 spi1 scs1 pwm3 mat5 extbus a5 p1[4]/scs2[2]/ pmat3[4]/a4 71 [1] gpio 1, pin 4 spi2 scs2 pwm3 mat4 extbus a4 trst 72 [1] ieee 1149.1 test rese t not; active low; pulled up internally rst 73 [1] asynchronous device reset; active low; pulled up internally v ss(osc) 74 ground for oscillator xout_osc 75 [2] crystal out for oscillator xin_osc 76 [2] crystal in for oscillator v dd(osc) 77 1.8 v supply for oscillator v ss(pll) 78 ground for pll p2[7]/mat1[3]/ ei3/d15 79 [1] gpio 2, pin 7 timer1 mat3 extint3 extbus d15 p3[14]/sdi1/ ei6/txdc0 80 [1] gpio 3, pin 14 spi1 sdi extint6 can0 txd p3[15]/sck1/ ei7/rxdc0 81 [1] gpio 3, pin 15 spi1 sck extint7 can0 rxd table 3. lqfp144 pin assignment ?continued pin name pin description default function function 1 function 2 function 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 9 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin v dd(io) 82 3.3 v power supply for i/o p2[8]/ clk_out/ pmat0[0]/ scs0[2] 83 [1] gpio 2, pin 8 clk_out pwm0 mat0 spi0 scs2 p2[9]/pmat0[1]/ scs0[1] 84 [1] gpio 2, pin 9 - pwm0 mat1 spi0 scs1 p1[3]/scs2[1]/ pmat3[3]/a3 85 [1] gpio 1, pin 3 spi2 scs1 pwm3 mat3 extbus a3 p1[2]/scs2[3]/ pmat3[2]/a2 86 [1] gpio 1, pin 2 spi2 scs3 pwm3 mat2 extbus a2 p1[1]/ei1/ pmat3[1]/a1 87 [1] gpio 1, pin 1 extint1 pwm3 mat1 extbus a1 v ss(core) 88 ground for digital core v dd(core) 89 1.8 v power supply for digital core p1[0]/ei0/ pmat3[0]/a0 90 [1] gpio 1, pin 0 extint0 pwm3 mat0 extbus a0 p2[10]/ pmat0[2]/ scs0[0] 91 [1] gpio 2, pin 10 - pwm0 mat2 spi0 scs0 p2[11]/ pmat0[3]/sck0 92 [1] gpio 2, pin 11 - pwm0 mat3 spi0 sck p0[0]/phb0/ txdc0/d24 93 [1] gpio 0, pin 0 qei0 phb can0 txd extbus d24 v ss(io) 94 ground for i/o p0[1]/pha0/ rxdc0/d25 95 [1] gpio 0, pin 1 qei 0 pha can0 rxd extbus d25 p0[2]/ clk_out/ pmat0[0]/d26 96 [1] gpio 0, pin 2 clk_out pwm0 mat0 extbus d26 p0[3]/pmat0[1]/ d27 97 [1] gpio 0, pin 3 - pwm0 mat1 extbus d27 p3[0]/pmat2[0]/ cs6 98 [1] gpio 3, pin 0 - pwm2 mat0 extbus cs6 p3[1]/pmat2[1]/ cs7 99 [1] gpio 3, pin 1 - pwm2 mat1 extbus cs7 p2[12]/ pmat0[4]/sdi0 100 [1] gpio 2, pin 12 - pwm0 mat4 spi0 sdi p2[13]/ pmat0[5]/ sdo0 101 [1] gpio 2, pin 13 - pwm0 mat5 spi0 sdo p0[4]/pmat0[2]/ d28 102 [1] gpio 0, pin 4 - pwm0 mat2 extbus d28 p0[5]/pmat0[3]/ d29 103 [1] gpio 0, pin 5 - pwm0 mat3 extbus d29 v dd(io) 104 3.3 v power supply for i/o table 3. lqfp144 pin assignment ?continued pin name pin description default function function 1 function 2 function 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 10 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin p0[6]/ pmat0[4]/d30 105 [1] gpio 0, pin 6 - pwm0 mat4 extbus d30 p0[7]/ pmat0[5]/d31 106 [1] gpio 0, pin 7 - pwm0 mat5 extbus d31 v dda(adc3v3) 107 3.3 v power supply for adc jtagsel 108 [1] tap controller select input; low-level selects the arm debug mode; high-level selects boundary scan; pulled up internally. n.c. 109 not connected to a function, must be tied to 3.3 v power supply for adc v dda(adc3v3) . vrefp 110 [2] high reference for adc vrefn 111 [2] low reference for adc p0[8]/in1[0]/tx dl0/a20 112 [3] gpio 0, pin 8 adc1 in0 lin0/uart txd extbus a20 p0[9]/in1[1]/ rxdl0/a21 113 [3] gpio 0, pin 9 adc1 in1 lin0/uart rxd extbus a21 p0[10]/in1[2]/ pmat1[0]/a8 114 [3] gpio 0, pin 10 adc1 in2 pwm1 mat0 extbus a8 p0[11]/in1[3]/ pmat1[1]/a9 115 [3] gpio 0, pin 11 adc1 in3 pwm1 mat1 extbus a9 p2[14]/sda1/ pcap0[0]/bls0 116 [1] gpio 2, pin 14 i2c1 sda pwm0 cap0 extbus bls0 p2[15]/scl1/ pcap0[1]/bls1 117 [1] gpio 2, pin 15 i2c1 scl pwm0 cap1 extbus bls1 p3[2]/mat3[0]/ pmat2[2] 118 [1] gpio 3, pin 2 timer3 mat0 pwm2 mat2 - v ss(io) 119 ground for i/o p3[3]/mat3[1]/ pmat2[3] 120 [1] gpio 3, pin 3 timer3 mat1 pwm2 mat3 - p0[12]/in1[4]/ pmat1[2]/a10 121 [3] gpio 0, pin 12 adc1 in4 pwm1 mat2 extbus a10 p0[13]/in1[5]/ pmat1[3]/a11 122 [3] gpio 0, pin 13 adc1 in5 pwm1 mat3 extbus a11 p0[14]/in1[6]/ pmat1[4]/a12 123 [3] gpio 0, pin 14 adc1 in6 pwm1 mat4 extbus a12 p0[15]/in1[7]/ pmat1[5]/a13 124 [3] gpio 0, pin 15 adc1 in7 pwm1 mat5 extbus a13 p0[16]in2[0]/ txd0/a22 125 [3] gpio 0, pin 16 adc2 in0 uart0 txd extbus a22 p0[17]/in2[1]/ rxd0/a23 126 [3] gpio 0, pin 17 adc2 in1 uart0 rxd extbus a23 v dd(core) 127 1.8 v power supply for digital core v ss(core) 128 ground for digital core p2[16]/txd1/ pcap0[2]/bls2 129 [1] gpio 2, pin 16 uart1 txd pwm0 cap2 extbus bls2 p2[17]/rxd1/ pcap1[0]/bls3 130 [1] gpio 2, pin 17 uart1 rxd pwm1 cap0 extbus bls3 table 3. lqfp144 pin assignment ?continued pin name pin description default function function 1 function 2 function 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 11 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin [1] bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5v tolerant; ttl with hysteresis; programmab le pull-up / pull-down / repeater. [2] analog pad; analog i/o [3] analog pad. 6. functional description 6.1 architectural overview the lpc2917/2919/01 consists of: ? an arm968e-s processor with real-time emulation support ? an amba multi-layer advanc ed high-performance bus (ahb) for interfacing to the on-chip memory controllers ? two dtl buses (an universal nxp interface) for interfacing to th e interrupt controller and the power, clock and reset control cluster (also called subsystem). v dd(io) 131 3.3 v power supply for i/o p0[18]/in2[2]/ pmat2[0]/a14 132 [3] gpio 0, pin 18 adc2 in2 pwm2 mat0 extbus a14 p0[19]/in2[3]/ pmat2[1]/a15 133 [3] gpio 0, pin 19 adc2 in3 pwm2 mat1 extbus a15 p3[4]/mat3[2]/ pmat2[4]/ txdc1 134 [1] gpio 3, pin 4 timer3 mat2 pwm2 mat4 can1 txd p3[5]/mat3[3]/ pmat2[5]/ rxdc1 135 [1] gpio 3, pin 5 timer3 mat3 pwm2 mat5 can1 rxd p2[18]/scs2[1]/ pcap1[1]/d16 136 [1] gpio 2, pin 18 spi2 scs1 pwm1 cap1 extbus d16 p2[19]/scs2[0]/ pcap1[2]/d17 137 [1] gpio 2, pin 19 spi2 scs0 pwm1 cap2 extbus d17 p0[20]/in2[4]/ pmat2[2]/a16 138 [3] gpio 0, pin 20 adc2 in4 pwm2 mat2 extbus a16 p0[21]/in2[5]/ pmat2[3]/a17 139 [3] gpio 0, pin 21 adc2 in5 pwm2 mat3 extbus a17 p0[22]/in2[6]/ pmat2[4]/a18 140 [3] gpio 0, pin 22 adc2 in6 pwm2 mat4 extbus a18 v ss(io) 141 ground for i/o p0[23]/in2[7]/ pmat2[5]/a19 142 [3] gpio 0, pin 23 adc2 in7 pwm2 mat5 extbus a19 p2[20]/ pcap2[0]/d18 143 [1] gpio 2, pin 20 spi2 sdo pwm2 cap0 extbus d18 tdi 144 [1] ieee 1149.1 data in, pulled up internally table 3. lqfp144 pin assignment ?continued pin name pin description default function function 1 function 2 function 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 12 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? three arm peripheral buse s (apb - a compatible superset of arm's amba advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems. ? one arm peripheral bus for even t router and system control. the lpc2917/2919/01 configures the arm968e- s processor in little-endian byte order. all peripherals run at their own clock frequency to optimize the total system power consumption. the ahb2apb bridge used in the subsystems co ntains a write-ahead buffer one transaction deep. this implies that when the arm968e-s issues a buffered write action to a register located on the apb side of the bridge, it continues even though the actual write may not yet have taken place. completion of a second write to the same subsystem will not be executed until the first write is finished. 6.2 arm968e-s processor the arm968e-s is a general purpose 32-bit risc processor, which offers high performance and very low power consumpt ion. the arm architecture is based on reduced instruction set comput er (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers (cisc). this simplic ity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective controller core. amongst the most com pelling features of the arm968e-s are: ? separate directly connected instruction and data tightly coupled memory (tcm) interfaces ? write buffers for the ahb and tcm buses ? enhanced 16 32 multiplier capable of single-cycle mac operations and 16-bit fixed- point dsp instructions to a ccelerate signal-processing algorithms and applications. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. the arm968e-s is based on the armv5te five-stage pipeline architecture. typically, in a three-stage pipeline architecture, while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory. in the five-stage pipeline additional stages are added for memory access and write-back cycles. the arm968e-s processor also employs a unique architectural strategy known as thumb, which makes it idea lly suited to high-volume applications with memory restrictions or to applications where code density is an issue. the key idea behind thumb is that of a supe r-reduced instruction set. essentially, the arm968e-s processor has two instruction sets: ? standard 32-bit armv5te set ? 16-bit thumb set the thumb set's 16-bit instruction length allo ws it to approach twice the density of standard arm code while retaining most of the arm's performance advantage over a traditional 16-bit controller using 16-bit regi sters. this is possib le because thumb code operates on the same 32-bit register set as arm code.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 13 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin thumb code can provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm controller connected to a 16-bit memory system. the arm968e-s processor is described in detail in the arm968e-s data sheet ref. 2 . 6.3 on-chip flash memory system the lpc2917/2919/01 includes a 512 kb or 768 kb flash memory system. this memory can be used for both code and data storage. programming of the flash memory can be accomplished via the flash memory controller or jtag. the flash controller also su pports a 16 kb, byte-accessibl e on-chip eeprom integrated on the lpc2917/2919/01. 6.4 on-chip static ram in addition to the two 16 kb tcms the lpc2917/2919/01 includes two static ram memories: one of 32 kb and one of 16 kb. both may be used for code and/or data storage. in addition, 8 kb sram for the etb can be used as static memory for code and data storage. however, dma access to this memory region is not supported.
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 14 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.5 memory map fig 3. lpc2917/2919/01 memory map 16 mb external static memory bank 0 16 mb external static memory bank 1 external static memory banks 7 to 2 reserved dma interface to tcm pcr/vic control 0x0000 0000 0 gb 1 gb 4 gb 2 gb 0x4000 0000 0x4100 0000 0x4300 0000 0x4200 0000 0x2000 0000 0x6000 0000 0x6000 4000 0x8000 0000 0x8000 8000 0x8000 c000 0xe000 0000 0xe002 0000 0xe004 0000 0xe006 0000 0xe008 0000 0xe00a 0000 0xe00c 0000 0xe00e 0000 0xe010 0000 0xe014 0000 0xe018 3000 0xf000 0000 0xf080 0000 0xffff 8000 0xffff ffff reserved reserved reserved reserved reserved reserved reserved peripheral subsystem #0 peripheral subsystem #2 peripheral subsystem #4 peripheral subsystem #6 0xe018 2000 0xe018 0000 32 kb ahb sram 16 kb ahb sram reserved reserved dma controller 8 kb etb sram etb control reserved itcm/dtcm on-chip flash 0x2020 4000 0x0000 0000 0x0040 0000 0x0000 4000 0x0040 4000 0x0080 0000 0x2000 0000 16 kb itcm 16 kb dtcm reserved reserved no physical memory peripherals #6 mscss subsystem itcm/dtcm memory sma controller peripherals #2 peripheral subsystem 0xe004 1000 0xe004 2000 0xe004 3000 0xe004 4000 0xe004 6000 0xe004 8000 0xe004 a000 0xe004 b000 0xe004 d000 0xe004 e000 0xe006 0000 0xe004 c000 0xe004 9000 0xe004 7000 0xe004 5000 0xe004 0000 spi0 wdt timer0 timer1 timer2 timer3 uart0 uart1 spi1 spi2 gpio0 gpio1 gpio2 gpio3 peripherals #0 general subsystem 0xe000 1000 0xe000 2000 0xe000 2000 0xe002 0000 0xe000 0000 cfid scu event router peripherals #4 networking subsystem 0xe008 1000 0xe008 0000 can0 can1 0xe008 2000 0xe008 3000 0xe008 4000 0xe008 7000 0xe008 9000 0xe008 b000 0xe00a 0000 0xe008 a000 0xe008 8000 0xe008 6000 i2c0 i2c1 reserved can id lut can common regs lin0 lin1 can af regs 0xe00c 0000 0xe00c 1000 0xe00c 2000 0xe00c 3000 0xe00c 4000 0xe00c 5000 0xe00c 6000 0xe00c 7000 0xe00c 8000 0xe00c 9000 0xe00c a000 0xe00e 0000 reserved adc1 adc2 pwm0 pwm1 pwm3 quadrature encoder pwm2 mscss timer0 mscss timer1 pcr/vic subsystem 0xffff 8000 0xffff 9000 0xffff a000 0xffff b000 0xffff c000 0xffff f000 0xffff ffff pmu cgu1 reserved reserved reserved reserved reserved vic cgu0 rgu 512 mb shadow area remappable to shadow area lpc2917/2919/01 002aad96 3 0x2008 0000 512 kb on-chip flash 768 kb on-chip flash flash controller 0x2000 0000 reserved 0x200c 0000 0x2020 0000 0x2020 4000 flash memory
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 15 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.6 reset, debug, test, and power description 6.6.1 reset and power-up behavior the lpc2917/2919/01 contains external reset input and internal power-up reset circuits. this ensures that a reset is extended internally unt il the oscillators an d flash have reached a stable state. see section 8 for trip levels of the in ternal power-up reset circuit 1 . see section 9 for characteristics of the several start-up and initialization times. table 4 shows the reset pin. at activation of the rst pin the jtagsel pin is sensed as logic low. if this is the case the lpc2917/2919/01 is assumed to be connected to debug hardware, and internal circuits re-program the source for the base_ sys_clk to be the crys tal oscillator instead of the low-power ring o scillator (lp_osc). this is requir ed because the clock rate when running at lp_osc speed is too low for the external debugging environment. 6.6.2 reset strategy the lpc2917/2919/01 contains a central module, the reset generator unit (rgu) in the power, clock and reset subsystem (pcrss), wh ich controls all internal reset signals towards the peripheral modules. the rgu provides individual reset control as well as the monitoring functions needed for tracing a reset back to source. 6.6.3 ieee 1149.1 interface pins (jtag boundary-scan test) the lpc2917/2919/01 contains boundary-scan te st logic according to ieee 1149.1, also referred to in this document as joint test action group (jtag). the boundary-scan test pins can be used to connect a debugger probe for the embedded arm processor. pin jtagsel selects between boundary-scan mode and debug mode. ta b l e 5 shows the boundary- scan test pins. 1. only for 1.8 v power sources table 4. reset pin symbol direction description rst in external reset input, active low; pulled up internally table 5. ieee 1149.1 boundary-scan test and debug interface symbol description jtagsel tap controller select input. low level selects arm debug mode and high level selects boundary scan and flash programming; pulled up internally trst test reset input; pulled up internally (active low) tms test mode select input; pulled up internally tdi test data input, pulled up internally tdo test data output tck test clock input
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 16 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.6.3.1 etm/etb the etm provides real-time trace capabilit y for deeply embedded processor cores. it outputs information about processor executio n to a trace buffer. a software debugger allows configuration of the etm using a jtag interface and displays the trace information that has been captured in a format that a user can easily understand. the etb stores trace data produced by the etm. the etm/etb module has the following features: ? closely tracks the instructions th at the arm core is executing. ? on-chip trace data storage (etb). ? all registers are programmed through jtag interface. ? does not consume power when trace is not being used. ? thumb/java instruction set support. 6.6.4 power supply pins ta b l e 6 shows the power supply pins. 6.7 clocking strategy 6.7.1 clock architecture the lpc2917/2919/01 contains several different internal clock areas. peripherals like timers, spi, uart, can and lin have their own individual clock sources called base clocks. all base clocks are generated by th e clock generator unit (cgu0). they may be unrelated in frequency and phase and can ha ve different clock sources within the cgu. the system clock for the cpu and ahb bus infr astructure has its own base clock. this means most peripherals are clocked independently from the system clock. see figure 4 for an overview of the clock areas within the device. within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. all branch clocks are outputs of the power management unit (pmu) and can be contro lled independently. br anch clocks derived from the same base clock are synchronous in frequency and phase. see section 6.15 for more details of clock and po wer control within the device. table 6. power supply pins symbol description v dd(core) digital core supply 1.8 v v ss(core) digital core ground (digital core, adc1/2) v dd(io) i/o pins supply 3.3 v v ss(io) i/o pins ground v dd(osc) oscillator and pll supply v ss(osc) oscillator ground v dda(adc3v3) adc1 and adc2 3.3 v supply v ss(pll) pll ground
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 17 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin two of the base clocks generated by the cgu0 are used as input into a second, dedicated cgu (cgu1). the cgu1 uses its ow n pll and fractional divider to generate the base clock for an independent clock output. fig 4. lpc2917/2919/01 block diag ram, overview of clock areas timer0/1 mtmr pwm0/1/2/3 adc1/2 qei modulation and sampling control subsystem base_mscss_clk branch clocks branch clocks base_adc_clk ba se_iclk0_clk base_iclk1_clk can0/1 global acceptance filter lin0/1 i2c0/1 networking subsystem base_ivnss_clk branch clocks branch clock reset/clock generation and power management power control subsystem base_pcr_clk branch clock gpio0/1/2/3 timer 0/1/2/3 spi0/1/2 uart0/1 wdt base_sys_clk cpu ahb multilayer matrix vic gpdma flash/sram/smc general subsytem peripheral subsystem ahb to apb bridges system control event router cfid branch clocks base_safe_clk base_uart_clk base_spi_clk base_tmr_clk 002aad962 cgu0 cgu1 base_out_clk clock out
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 18 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.7.2 base clock and branch clock relationship ta b l e 7 and ta b l e 8 contain an overview of all the base blocks in the lpc2917/2919/01 and their derived branch clocks. in relevant cases more detailed information can be found in the specific subsystem desc ription. some branch clocks ha ve special protection since they clock vital system parts of the device an d should (for example) not be switched off. see section 6.15.5 for more details of how to control the individual branch clocks. table 7. cgu0 generated base clock and branch clock overview base clock branch clock name parts of the device clocked by this branch clock remark base_safe_clk clk_safe watchdog timer [1] base_sys_clk clk_sys_cpu arm968e-s and tcms clk_sys_sys ahb bus infrastructure clk_sys_pcrss ahb side of bridge in pcrss clk_sys_fmc flash-memory controller clk_sys_ram0 embedded sram controller 0 (32 kb) clk_sys_ram1 embedded sram controller 1 (16 kb) clk_sys_smc external static-memory controller clk_sys_gess general subsystem clk_sys_vic vectored in terrupt controller clk_sys_pess peripheral subsystem [2] [4] clk_sys_gpio0 gpio bank 0 clk_sys_gpio1 gpio bank 1 clk_sys_gpio2 gpio bank 2 clk_sys_gpio3 gpio bank 3 clk_sys_ivnss_a ahb side of bridge of ivnss clk_sys_mscss_a ahb side of bridge of mscss clk_sys_dma gpdma base_pcr_clk clk_pcr_slow pcrss, cgu, rgu and pmu logic clock [1] , [3] base_ivnss_clk clk_ivnss_apb apb side of the ivnss clk_ivnss_canca can controller acceptance filter clk_ivnss_canc0 can channel 0 clk_ivnss_canc1 can channel 1 clk_ivnss_i2c0 i2c0 clk_ivnss_i2c1 i2c1 clk_ivnss_lin0 lin channel 0 clk_ivnss_lin1 lin channel 1
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 19 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin [1] this clock is always on (cannot be sw itched off for system safety reasons) [2] in the peripheral subsystem parts of the timers , watchdog timer, spi and uart have their own clock source. see section 6.12 for details. [3] in the power clock and reset control subsystem pa rts of the cgu, rgu, and pmu have their own clock source. see section 6.15 for details. [4] the clock should remain activated when syst em wake-up on timer or uart is required. base_mscss_clk clk_mscss_apb apb side of the mscss clk_mscss_mtmr0 timer 0 in the mscss clk_mscss_mtmr1 timer 1 in the mscss clk_mscss_pwm0 pwm 0 clk_mscss_pwm1 pwm 1 clk_mscss_pwm2 pwm 2 clk_mscss_pwm3 pwm 3 clk_mscss_adc1_apb apb side of adc 1 clk_mscss_adc2_apb apb side of adc 2 clk_mscss_qei quadrature encoder base_uart_clk clk_uart0 uart 0 interface clock clk_uart1 uart 1 interface clock base_iclk0_clk - cgu1 input clock base_spi_clk clk_spi0 spi 0 interface clock clk_spi1 spi 1 interface clock clk_spi2 spi 2 interface clock base_tmr_clk clk_tmr0 timer 0 clock for counter part clk_tmr1 timer 1 clock for counter part clk_tmr2 timer 2 clock for counter part clk_tmr3 timer 3 clock for counter part base_adc_clk clk_adc1 control of adc 1, capture sample result clk_adc2 control of adc 2, capture sample result reserved - - base_iclk1_clk - cgu1 input clock table 8. cgu1 base clock and branch clock overview base clock branch clock name parts of the device clocked by this branch clock base_out_clk clk_out_clk clockout pin table 7. cgu0 generated base clock and branch clock overview ?continued base clock branch clock name parts of the device clocked by this branch clock remark
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 20 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.8 flash memory controller the flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. the flash has to be programmed initially via jtag. in-system programming must be supported by the bootloader. in-application programming is possible. flash memory contents can be protected by disabling jtag access. suspension of burning or erasing is not supported. the flash memory controller (fmc) interfac es to the embedded flash memory for two tasks: ? memory data transfer ? memory configuration via triggering, programming, and erasing the key features are: ? programming by cpu via ahb ? programming by external programmer via jtag ? jtag access protection ? burn-finished and erase-finished interrupt 6.8.1 functional description after reset, flash initializati on is started, which takes t init time (see section 9 ). during this initialization, flash access is not possible and ahb transfers to flash are stalled, blocking the ahb bus. during flash initialization, the in dex sector is read to identify the status of the jtag access protection and sector security. if jtag acce ss protection is active, the flash is not accessible via jtag. in this case, arm debug facilities are disabled and flash-memory contents cannot be read. if sector security is active, only the unsecured sections can be read. flash can be read synchronously or asynchrono usly to the system clock. in synchronous operation, the flash goes into standby after returning the read data. started reads cannot be stopped, and speculative reading and dual buffering are therefore not supported. with asynchronous reading, transfer of the ad dress to the flash and of read data from the flash is done asynchronously, giving the fastes t possible response time. started reads can be stopped, so speculative reading and dual buffering are supported. buffering is offered because the flash has a 128-bit wide data interface while the ahb interface has only 32 bits. with buffering a buffer line holds the complete 128-bit flash word, from which four words can be read. without buffering every ahb data port read starts a flash read. a flash read is a slow process compared to the minimum ahb cycle time, so with buffering the average read ti me is reduced. this can improve system performance. with single buffering, the most recently re ad flash word remains available until the next flash read. when an ahb data-port read transfer requires data from the same flash word as the previous read transfer, no new flash read is done and the read data is given without wait cycles.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 21 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin when an ahb data port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. with dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer. on a primary buffer, hit data can be copied to the secondary buffer line, which a llows the flash to start a speculative read of the next flash word. both buffer lines are invalidated after: ? initialization ? configuration-register access ? data-latch reading ? index-sector reading the modes of operation are listed in ta b l e 9 . 6.8.2 pin description the flash memory controller has no external pins. however, the flash can be programmed via the jtag pins, see section 6.6.3 . 6.8.3 clock description the flash memory controller is clocked by clk_sys_fmc, see section 6.7.2 . 6.8.4 flash layout the arm processor can program the flash for isp (in-system programming) and iap (in- application programming). note that the flas h always has to be programmed by ?flash words? of 128 bits (four 32-bit ahb bus words, hence 16 bytes). the flash memory is organized into eight ?sma ll? sectors of 8 kb each and up to 11 ?large? sectors of 64 kb each. the number of large se ctors depends on the device type. a sector must be erased before data can be written to it. the flash memory also has sector-wise protection. writing occurs per page which consists of 4096 bits (32 flash words). a small sector contains 16 pages; a large sector contains 128 pages. table 9. flash read modes synchronous timing no buffer line for single (non-linear) reads; one flash-word read per word read single buffer line default mode of operation; most recently read flas h word is kept until another flash word is required asynchronous timing no buffer line one flash-word read per word read single buffer line most recently read flash word is kept until another flash word is required dual buffer line, single speculative on a buffer miss a flash read is done, followed by at most one speculative read; optimized for ex ecution of code with small loops (less than eight words) from flash dual buffer line, always speculative most recently used flash word is copied into second buffer line; next flash-word read is started; highest performance for linear reads
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 22 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ta b l e 1 0 gives an overview of the flash-sector base addresses. [1] availability of sector 15 to sector 18 depends on device type, see section 3 ? ordering information ? . the index sector is a special sector in which the jtag access protection and sector security are located. the address space bec omes visible by setting the fs_iss bit and overlaps the regular flash sector?s address space. note that the index sector cannot be erased, and that access to it has to be performed via code outside the flash. 6.8.5 flash bridge wait-states to eliminate the delay associated with sy nchronizing flash-read data, a predefined number of wait-states must be programmed. these depend on flash-memory response time and system clock period. the minimum wa it-states value can be calculated with the following formulas: synchronous reading: (1) asynchronous reading: (2) table 10. flash sector overview sector number sector size (kb) sector base address 11 8 0x2000 0000 12 8 0x2000 2000 13 8 0x2000 4000 14 8 0x2000 6000 15 8 0x2000 8000 16 8 0x2000 a000 17 8 0x2000 c000 18 8 0x2000 e000 0 64 0x2001 0000 1 64 0x2002 0000 2 64 0x2003 0000 3 64 0x2004 0000 4 64 0x2005 0000 5 64 0x2006 0000 6 64 0x2007 0000 7 [1] 64 0x2008 0000 8 [1] 64 0x2009 0000 9 [1] 64 0x200a 0000 10 [1] 64 0x200b 0000 wst t acc clk () t t tclk sys () ------------------ > 1 ? wst t acc addr () t tclk sys () --------------------- - > 1 ?
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 23 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin remark: if the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the ahb bus) if speculative reading is active. 6.8.6 eeprom eeprom is a non-volatile memo ry mostly used for storing relatively small amounts of data, for example for storing settings. it co ntains one 16 kb memory block and is byte-programmable and byte-erasable. the eeprom can be accessed only through the flash controller. 6.9 external static memory controller the lpc2917/2919/01 contains an external static memory controller (smc) which provides an interface for external (off-chip) memory devices. key features are: ? supports static memory-mapped devices in cluding ram, rom, flash, burst rom and external i/o devices. ? asynchronous page-mode read operation in non-clocked memory subsystems. ? asynchronous burst-mode read a ccess to burst-mode rom devices. ? independent configuration for up to eight banks, each up to 16 mb. ? programmable bus-turnaround (idle) cycles (one to 16). ? programmable read and write wait states (up to 32), for static ram devices. ? programmable initial and subsequent burst- read wait state for burst-rom devices. ? programmable write protection. ? programmable burst-mode operation. ? programmable external data width: 8 bits, 16 bits or 32 bits. ? programmable read-byte lane enable control. 6.9.1 description the smc simultaneously supports up to eigh t independently configur able memory banks. each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting sram, rom, burst-rom memory , or external i/o devices. a separate chip select output is available for each bank. the chip select lines are configurable to be active high or low. me mory-bank selection is controlled by memory addressing. table 11 shows how the 32-bit system address is mapped to the external bus memory base addresses, chip selects, and bank internal addresses.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 24 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.9.2 pin description the external static-memory controller modul e in the lpc2917/2919/01 has the following pins, which are combined with other functions on the port pi ns of the lpc2917/2919/01. ta b l e 1 3 shows the external memory controller pins. 6.9.3 clock description the external static-mem ory controller is clock ed by clk_sys_smc, see section 6.7.2 . 6.9.4 external memory timing diagrams a timing diagram for reading from external memory is shown in figure 5 . the relationship between the wait-state settings is indicated with arrows. table 11. external memory-bank address bit description 32-bit system address bit field symbol description 31 to 29 ba[2:0] external static-memory base address (three most significant bits); the base address can be found in the memory map; see ref. 1 . this field contains ?010? when addressing an external memory bank. 28 to 26 cs[2:0] chip select address space for eight memory banks; see ref. 1 . 25 and 24 - always ?00?; other values are ?mirrors? of the 16 mb bank address. 23 to 0 a[23:0] 16 mb memory banks address space table 12. external static-memory controller banks cs[2:0] bank 000 bank 0 001 bank 1 010 bank 2 011 bank 3 100 bank 4 101 bank 5 110 bank 6 111 bank 7 table 13. external memory controller pins symbol direction description extbus csx out memory-bank x select, x runs from 0 to 7 extbus blsy out byte-lane select input y, y runs from 0 to 3 extbus we out write enable (active low) extbus oe out output enable (active low) extbus a[23:0] out address bus extbus d[31:0] in/out data bus
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 25 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin a timing diagram for writing to external memory is shown in figure 6 . the relationship between wait-state settings is indicated with arrows. wstoen = 3, wst1 = 6 fig 5. reading from external memory wstwen = 3, wst2 = 7 (1) bls has the same timing as we in configurations that use t he byte lane enable signals to connect to write enable (8 bit devices). fig 6. writing to external memory oe clk(sys) cs a d wstoen wst1 002aae70 4 bls clk(sys) cs a d wst2 wstwen 002aae70 5 we/bls (1)
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 26 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin usage of the idle/turn-around time (idcy) is demonstrated in figure 7 . extra wait states are added between a read and a write cycle in the same external memory device. address pins on the device are shared with other functions. when connecting external memories, check that the i/o pin is programme d for the correct function. control of these settings is handled by the scu. 6.10 dma controller the dma controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one st ream for transmit and one for receives. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same ahb master or one area by each master. the dma controls eight dma channels with ha rdware prioritization. the dma controller interfaces to the system via two ahb bus masters, each with a full 32-bit data bus width. dma operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. incrementing or non-incrementing addressing for source and destination are supported, as well as programmable dma burst size. scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not have to occupy contiguous areas of memory. 6.10.1 dma support for peripherals the gpdma supports the following peripheral s: spi0/1/2 and uart 0/1. the gpdma can access both embedded sram blocks (16 kb and 32 kb), both tcms, external static memory, and flash memory. wstoen = 2, wstwen = 4, wst1 = 6, wst2 = 4, idcy = 5 fig 7. reading/writing external memory oe clk(sys) cs a d wstoen wst1 wstwen wst2 idcy 002aae706 we
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 27 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.10.2 clock description the dma controller is clocked by clk_ sys_dma derived fr om base_sys_clk, see section 6.7.2 . 6.11 general subsystem 6.11.1 general subsystem clock description the general subsystem is clocked by clk_sys_gess, see section 6.7.2 . 6.11.2 chip and feature identification the chip/feature id (cfid) module contains registers which show and control the functionality of the chip. it contains an id to identify the silic on and also registers containing information about the featur es enabled or disabled on the chip. the key features are: ? identification of product ? identification of features enabled the cfid has no external pins. 6.11.3 system control unit (scu) the system control unit contains system-relat ed functions.the key feat ure is configuration of the i/o port-pins multiplexer. it defines the function of each i/o pin of the lpc2917/2919/01. the i/o pin configuration shou ld be consistent with peripheral function usage. the scu has no external pins. 6.11.4 event router the event router provides bus- controlled routing of input even ts to the vectored interrupt controller for use as interrupt or wake-up signals. key features: ? up to 19 level-sensitive exte rnal interrupt pins, including the receive pins of spi, can, lin, and uart, as well as the i 2 c-bus scl pins plus three internal event sources. ? input events can be used as interrup t source either di rectly or latched (edge-detected). ? direct events disappear when the event becomes inactive. ? latched events remain active until they are explicitly cleared. ? programmable input level and edge polarity. ? event detection maskable. ? event detection is fully asynchronous, so no clock is required. the event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. the event router can be used to start a clock on an external event.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 28 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin the vectored interrupt-controller inputs are active high. 6.11.4.1 pin description the event router module in the lpc2917/2919/ 01 is connected to the pins listed below. the pins are combined with other function s on the port pins of the lpc2917/2919/01. ta b l e 1 4 shows the pins connected to the event router, and also the corresponding bit position in the event-router registers and the default polarity. 6.12 peripheral subsystem 6.12.1 peripheral subsystem clock description the peripheral subsyste m is clocked by a number of different clocks: ? clk_sys_pess ? clk_uart0/1 ? clk_spi0/1/2 ? clk_tmr0/1/2/3 ? clk_safe see section 6.7.2 6.12.2 watchdog timer the purpose of the watchdog timer is to reset the arm9 processor within a reasonable amount of time if the processor enters an error state. the watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time. key features: ? internal chip reset if not periodically triggered ? timer counter register runs on always-on safe clock table 14. event-router pin connections symbol direction description default polarity extint 7 - 0 in external interrupt input 7 - 0 1 can0 rxd in can0 receive data input wake-up 0 can1 rxd in can1 receive data input wake-up 0 i2c0_scl in i2c0 scl clock input 0 i2c1_scl in i2c1 scl clock input 0 lin0 rxd in lin0 receive data input wake-up 0 lin1 rxd in lin1 receive data input wake-up 0 spi0 sdi in spi0 receive data input 0 spi1 sdi in spi1 receive data input 0 spi2 sdi in spi2 receive data input 0 uart0 rxd in uart0 receive data input 0 uart1 rxd in uart1 receive data input 0 - na can interrupt (internal) 1 - na vic fiq (internal) 1 - na vic irq (internal) 1
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 29 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? optional interrupt generation on watchdog time-out ? debug mode with disabling of reset ? watchdog control register change-protected with key ? programmable 32-bit watchdog timer period with programmable 32-bit prescaler. 6.12.2.1 functional description the watchdog timer consists of a 32-bit counter with a 32-bit prescaler. the watchdog should be programmed with a time-out value and then periodically restarted. when the watchdog times out, it generates a reset through the rgu. to generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled via the interrupt enable register. a watchdog-ov erflow interrupt can be cleared by writing to the clear-interrupt register. another way to prevent resets during debu g mode is via the pause feature of the watchdog timer. the watchdog is stalled when the arm9 is in debug mode and the pause_enable bit in the watchdog timer control register is set. the watchdog reset output is fed to the reset generator unit (rgu). the rgu contains a reset source register to identify the reset source when the device has gone through a reset. see section 6.15.4 . 6.12.2.2 clock description the watchdog timer is clocked by two di fferent clocks; clk_sys_pess and clk_safe, see section 6.7.2 . the register interface towards the system bus is clocked by clk_sys_pess. the timer and prescale counters are cloc ked by clk_safe which is always on. 6.12.3 timer the lpc2917/2919/01 contains six identical ti mers: four in the peripheral subsystem and two in the modulation and sampling control subsystem (mscss) located at different peripheral base addresses. this section de scribes the four timers in the peripheral subsystem. each timer has four capture in puts and/or match outputs. connection to device pins depends on the configuration programmed into the port function-select registers. the two timers located in the msc ss have no external capture or match pins, but the memory map is identical, see section 6.14.6 . one of these timers has an external input for a pause function. the key features are: ? 32-bit timer/counter with programmable 32-bit prescaler ? up to four 32-bit capture channels per timer. these take a snapshot of the timer value when an external signal connected to th e timerx capn input changes state. a capture event may also optionally generate an interrupt ? four 32-bit match registers per timer that allow: ? continuous operation with optional interrupt generation on match ? stop timer on match with optional interrupt generation ? reset timer on match with optional interrupt generation
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 30 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? up to four external outputs per timer co rresponding to match registers, with the following capabilities: ? set low on match ? set high on match ? toggle on match ? do nothing on match ? pause input pin (mscss timers only) the timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specif ied timer values, based on four match registers. they also include capture inputs to trap the timer value when an input signal changes state, optionally generating an interrupt. the core function of the timers consists of a 32 bit prescale counter triggering the 32 bit timer counter. both counters run on clock clk_tmrx (x runs from 0 to 3) and all time references are related to the period of this clock. note that each timer has its individual clock source within the peripheral subsystem. in the modulation and sampling subsystem each timer also has its own individual clock source. see section section 6.15.5 for information on generation of these clocks. 6.12.3.1 pin description the four timers in the peripheral subsyst em of the lpc2917/2919/01 have the pins described below. the two timers in the modulation and sampling subsystem have no external pins except for the pause pin on mscss timer 1. see section 6.14.6 for a description of these timers and their associ ated pins. the timer pins are combined with other functions on the port pi ns of the lpc2917/2919/01, see section 6.11.3 . table ta b l e 1 5 shows the timer pins (x runs from 0 to 3). 6.12.3.2 clock description the timer modules are clocked by two di fferent clocks; clk_sys_pess and clk_tmrx (x = 0-3), see section 6.7.2 . note that each timer has its own clk_tmrx branch clock for power management. the frequency of all these clocks is identical as they are derived from the same base clock base_clk_tmr. th e register interfac e towards the system bus is clocked by clk_sys_pess. the timer and prescale counte rs are clocked by clk_tmrx. table 15. timer pins symbol pin name direction description timerx cap[0] capx[0] in timer x capture input 0 timerx cap[1] capx[1] in timer x capture input 1 timerx cap[2] capx[2] in timer x capture input 2 timerx cap[3] capx[3] in timer x capture input 3 timerx mat[0] matx[0] out timer x match output 0 timerx mat[1] matx[1] out timer x match output 1 timerx mat[2] matx[2] out timer x match output 2 timerx mat[3] matx[3] out timer x match output 3
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 31 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.12.4 uarts the lpc2917/2919/01 contains two identical ua rts located at different peripheral base addresses. the key features are: ? 16-byte receive and transmit fifos. ? register locations conform to 550 industry standard. ? receiver fifo trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes. ? built-in baud rate generator. ? support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the uart is commonly used to implement a serial interface such as rs232. the lpc2917/2919/01 contains two industry-standa rd 550 uarts with 16-byte transmit and receive fifos, but they can also be put into 450 mode without fifos. 6.12.4.1 pin description the uart pins are combined with other functions on the port pins of the lpc2917/2919/01. ta b l e 1 6 shows the uart pins (x runs from 0 to 1). 6.12.4.2 clock description the uart modules are clocked by two different clo cks; clk_sys_pess and clk_uartx (x = 0-1), see section 6.7.2 . note that each uart has its own clk_uartx branch clock for power management. the frequen cy of all clk_uartx clocks is identical since they are derived fr om the same base clock base_clk_uart. the register interface towards the system bus is clocked by clk_sys_p ess. the baud generator is clocked by the clk_uartx. 6.12.5 serial peripheral interface (spi) the lpc2917/2919/01 contains three serial peripheral interface modules (spis) to allow synchronous serial communication with slave or master peripherals. the key features are: ? master or slave operation ? each spi supports up to four slaves in sequential multi-slave operation ? supports timer-triggered operation ? programmable clock bit rate and prescale based on spi source clock (base_spi_clk), independent of system clock ? separate transmit and receive fifo memo ry buffers; 16 bits wide, 32 locations deep ? programmable choice of interface operation: motorola spi or texas instruments synchronous serial interfaces ? programmable data-frame size from 4 to 16 bits table 16. uart pins symbol pin name direction description uartx txd txdx out uart channel x transmit data output uartx rxd rxdx in uart channel x receive data input
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 32 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? independent masking of transmit fifo, rece ive fifo and receive overrun interrupts ? serial clock-rate mast er mode: fserial_clk f clk(spi) /2 ? serial clock-rate slav e mode: fserial_clk = f clk(spi) /4 ? internal loopback test mode the spi module can operate in: ? master mode: ? normal transmission mode ? sequential slave mode ? slave mode 6.12.5.1 functional description the spi module is a master or slave interf ace for synchronous serial communication with peripheral devices that have either motorola spi or texas instruments synchronous serial interfaces. the spi module performs serial-to-parallel conv ersion on data received from a peripheral device. the transmit and receive paths are buffered with fifo memories (16 bits wide 32 words deep). serial data is transmitted on pins sdox and received on pins sdix. the spi module includes a programmable bit-ra te clock divider and prescaler to generate the spi serial clock from the input clock clk_spix. the spi module?s operating mode, frame format, and word size are programmed through the slvn_settings registers. a single combined interrupt request spi_intreq output is asserted if any of the interrupts are asserted and unmasked. depending on the operating mode selected , the spi scs outputs operate as an active-high frame synchronization output for texas instruments synchronous serial frame format or an active low chip select for spi. each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the msb. 6.12.5.2 pin description the spi pins are combined with other functions on the port pins of the lpc2917/2919/01, see section 6.11.3 . ta b l e 1 7 shows the spi pins (x runs from 0 to 2; y runs from 0 to 3). [1] direction of spix scs and spix sck pins depends on master or slave mode. these pins are output in master mode, input in slave mode. [2] in slave mode there is only one chip select input pin, spix scs0. the other chip selects have no function in slave mode. table 17. spi pins symbol pin name direction description spix scsy scsx[y] in/out spix chip select [1] [2] spix sck sckx in/out spix clock [1] spix sdi sdix in spix data input spix sdo sdox out spix data output
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 33 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.12.5.3 clock description the spi modules are clocked by two di fferent clocks; clk_ sys_pess and clk_spix (x = 0, 1, 2), see section 6.7.2 . note that each spi has its own clk_spix branch clock for power management. the frequency of all clocks clk_spix is identical as they are derived from the same base clock base_clk_spi. the register interface to wards the system bus is clocked by clk_sys_pess. the serial-clo ck rate divisor is clocked by clk_spix. the spi clock frequency can be controlled by the cgu. in master mode the spi clock frequency (clk_spix) must be set to at least twice the spi serial clock rate on the interface. in slave mode clk_spix must be set to four times the spi serial clock rate on the interface. 6.12.6 general-purpose i/o the lpc2917/2919/01 contains four general-purpose i/o ports located at different peripheral base addresses. all i/o pins are bidirectional, and the direction can be programmed individually. the i/o pad behavior depends on the configuration programmed in the port function-select registers. the key features are: ? general-purpose parallel inputs and outputs ? direction control of individual bits ? synchronized input sampling for stable input-data values ? all i/o defaults to input at reset to avoid any possible bus conflicts 6.12.6.1 functional description the general-purpose i/o provides individual c ontrol over each bidirectional port pin. there are two registers to control i/o direction and output level. the inputs are synchronized to achieve stable read-levels. to generate an open-drain output, set the bit in the output register to the desired value. use the direction register to control the signa l. when set to outpu t, the output driver actively drives the value on the output: when set to input the signal floats and can be pulled up internally or externally. 6.12.6.2 pin description the five gpio ports in the lpc2917/2919/01 have the pins listed below. the gpio pins are combined with other functions on the port pins of the lpc2917/2919/01. ta b l e 1 8 shows the gpio pins. table 18. gpio pins symbol pin name direction description gpio0 pin[31:0] p0[31:0] in/out gpio port x pins 31 to 0 gpio1 pin[31:0] p1[31:0] in/out gpio port x pins 31 to 0 gpio2 pin[27:0] p2[27:0] in/out gpio port x pins 27 to 0 gpio3 pin[15:0] p3[15:0] in/out gpio port x pins 15 to 0
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 34 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.12.6.3 clock description the gpio modules are clocked by several clocks, all of which are derived from base_sys_clk; clk_sys_pess and clk_sys_gp iox (x = 0, 1, 2, 3), see section 6.7.2 . note that each gpio has its ow n clk__sys_gpiox branch clock for power management. the frequency of all cl ocks clk_sys_gpiox is identical to clk_sys_pess since they are derived from the same base clock base_sys_clk. 6.13 networking subsystem 6.13.1 can gateway controller area network (can) is the definition of a high-performance communication protocol for serial data communication. th e two can controllers in the lpc2917/2919/01 provide a full implementation of t he can protocol according to the can specification version 2.0b . the gateway concept is fully scalable with the number of can controllers, and always operates together with a separate powerful and flexible hardware acceptance filter. the key features are: ? supports 11-bit as well as 29-bit identifiers ? double receive buffer and triple transmit buffer ? programmable error-warning limit and error counters with read/write access ? arbitration-lost capture and error-code capture with detailed bit position ? single-shot transmission (i.e. no re-transmission) ? listen-only mode (no acknowledge; no active error flags) ? reception of ?own? message s (self-reception request) ? fullcan mode for message reception 6.13.1.1 global acceptance filter the global acceptance filter provides look-up of received identifiers - called acceptance filtering in can terminology - for all the can controllers. it in cludes a can id look-up table memory, in which software maintains one to five sections of identifiers. the can id look-up table memory is 2 kb large (512 words, each of 32 bits). it can contain up to 1024 standard frame identifiers or 512 extended frame identifiers or a mixture of both types. it is also possible to define identifier groups for standard and extended message formats. 6.13.1.2 pin description the two can controllers in the lpc2917/2919/01 have the pins listed below. the can pins are combined with other functions on the port pi ns of the lpc2917/2919/01. ta b l e 1 9 shows the can pins (x runs from 0 to 1). table 19. can pins symbol pin name direction description canx txd txdc0/1 out can channel x transmit data output canx rxd rxdc0/1 in can channel x receive data input
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 35 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.13.2 lin the lpc2917/2919/01 contain two lin 2.0 ma ster controllers. these can be used as dedicated lin 2.0 master controllers with addi tional support for sync break generation and with hardware implementation of the li n protocol according to spec 2.0. remark: both lin channels can be also configured as uart channels. the key features are: ? complete lin 2.0 message handling and transfer ? one interrupt per lin message ? slave response time-out detection ? programmable sync-break length ? automatic sync-field an d sync-break generation ? programmable inter-byte space ? hardware or software parity generation ? automatic checksum generation ? fault confinement ? fractional baud rate generator 6.13.2.1 pin description the two lin 2.0 master controllers in the lpc2917/2919/01 have the pins listed below. the lin pins are combined with other functions on the port pins of the lpc2917/2919/01. ta b l e 2 0 shows the lin pins. for more information see ref. 1 subsection 3.43, lin master controller. 6.13.3 i 2 c-bus serial i/o controllers the lpc2917/2919/01 each contain two i 2 c-bus controllers. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or as a transmitter with the capability to both receive and send information (such as memory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus, and it can be controlled by more than one bus master connected to it. the main features if the i 2 c-bus interfaces are: ? i 2 c0 and i 2 c1 use standard i/o pins with bit rates of up to 400 kbit/s (fast i 2 c-bus) and do not support powering off of indivi dual devices connected to the same bus lines. ? easy to configure as master, slave, or master/slave. table 20. lin controller pins symbol pin name direction description lin0/1 txd txdl0/1 out lin channel 0/1 transmit data output lin0/1 rxd rxdl0/1 in lin channel 0/1 receive data input
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 36 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? all i 2 c-bus controllers support multiple address recognition and a bus monitor mode. 6.13.3.1 pin description [1] note that the pins are not i 2 c-bus compliant open-drain pins. 6.14 modulation and samp ling control subsystem the modulation and sampling control s ubsystem (mscss) in the lpc2917/2919/01 includes four pulse-width modulators (pwm s), two 10-bit successive approximation analog-to-digital converters (adcs) and two timers. the key features of the mscss are: ? two 10-bit, 400 ksamples/s, 8-channel adcs with 3.3 v inputs and various trigger- start options ? four 6-channel pwms (pulse-width modulators) with capture and trap functionality ? two dedicated timers to schedule and synchronize the pwms and adcs ? quadrature encoder interface 6.14.1 functional description the mscss contains pulse-width modulator s (pwms), analog-to-digital converters (adcs) and timers. figure 8 provides an overview of the mscss. an ahb-to-apb bus bridge takes care of communication with the ahb system bus. two internal timers are dedicated to this subsystem. mscss timer 0 can be used to generate start pulses for the adcs and the first pwm. the second timer (mscss timer 1) is used to generate ?carrier? signals for the pwms. these carrier patterns can be used, for example, in applications requiring current control. several other trigger possibilities are provided for the adcs (external, cascaded or following a pwm). the capture inputs of both timers can also be used to capture the start pulse of the adcs. table 21. i 2 c-bus pins [1] symbol pin name direction description i2c scl0/1 scl0/1 i/o i2 c clock input/output i2c sda0/1 sda0/1 i/o i2c data input/output
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 37 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin the pwms can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely. capt ure inputs are provided to measure event phases compared to the main counter. depending on the applications, these inputs can be connected to digital sensor motor outputs or digital external signals. interrupt signals are generated on several events to closely interact with the cpu. the adcs can be used for any application nee ding accurate digitized data from analog sources. to support applications like motor control, a mechanism to synchronize several pwms and adcs is availabl e (sync_in and sync_out). note that the pwms run on the pwm cloc k and the adcs on the adc clock, see section 6.15.2 .
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 38 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin fig 8. modulation and sampling control subsystem (mscss) block diagram 002aad96 1 pwm0 mat[5:0] pwm1 mat[5:0] pwm2 mat[5:0] pwm3 mat[5:0] pwm0 cap[2:0] pause mscss timer0 mscss timer1 adc1 adc2 pwm0 pwm1 adc1 in[7:0] adc2 in[7:0] adc2 ext start qei pwm1 cap[2:0] pwm2 trap pwm0 trap pwm1 trap pwm2 cap[2:0] pwm3 trap pwm3 cap[2:0] adc1 ext start start start start synch pwm2 synch pwm3 synch carrier carrier carrier carrier idx0 pha0 phb0 mscss ahb-to-apb bridge capture capture
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 39 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.14.2 pin description the pins of the lpc2917/2919/01 mscss a ssociated with the two adc modules are described in section 6.14.4.2 . pins connected to the four pwm modules are described in section 6.14.5.4 , pins directly connected to the mscss timer 1 module are described in section 6.14.6.1 , and pins connected to the quadrature encoder interface are described in section 6.14.7.1 . 6.14.3 clock description the mscss is clocked from a nu mber of different sources: ? clk_sys_mscss_a clocks the ahb si de of the ahb-to-apb bus bridge ? clk_mscss_apb clocks the subsystem apb bus ? clk_mscss_mtmr0/1 clocks the timers ? clk_mscss_pwm0..3 clocks the pwms. each adc has two clock areas; a apb part clocked by clk_ms css_adcx_apb (x = 1 or 2) and a control part for the analog section clocked by clk_adcx = 1 or 2), see section 6.7.2 . all clocks are derived from the base_ms css_clk, except fo r clk_sys_mscss_a which is derived form base_sys_clk, and th e clk_adcx clocks which are derived from base_clk_adc. if specific pwm or adc modules are not used their corresponding clocks can be switched off. 6.14.4 analog-to-digital converter the mscss in the lpc2917/2919/01 includ es two 10-bit successive-approximation analog-to-digital converters. the key features of the adc interface module are: ? adc1 and adc2: eight analog inputs; time -multiplexed; measurement range up to 3.3 v ? external reference-level inputs ? 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit resolution ? programmable resolution from 2-bit to 10-bit ? single analog-to-digital conversion scan mode and continuous analog-to-digital conversion scan mode ? optional conversion on transition on external start input, timer capture/match signal, pwm_sync or ?previous? adc ? converted digital values are stored in a register for each channel ? optional compare condition to generate a ?less than? or an ?equal to or greater than? compare-value indication for each channel ? power-down mode
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 40 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.14.4.1 functional description the adc block diagram, figure 9 , shows the basic architecture of each adc. the adc functionality is divided into two major parts; one part running on the mscss subsystem clock, the other on the adc clock. this split into two clock domains affects the behavior from a system-level perspective. the actual analog-to-digital conversions take place in the adc clock domain, but system control takes place in the system clock domain. a mechanism is provided to modify configurat ion of the adc and co ntrol the moment at which the updated configuration is transferred to the adc domain. the adc clock is limited to 4.5 mhz maximum frequency and should always be lower than or equal to the system clock frequency. to meet this constraint or to select the desired lower sampling frequency, the clock generation unit provides a programmable fractional system-clock divider dedicated to the adc clock. conversion rate is determined by the adc clock frequency divided by the number of resolution bits plus one. accessing adc registers requires an enabled adc cl ock, which is controllable via the clock generation unit, see section 6.15.2 . each adc has four start inputs . note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the adc domain. the start inputs are connected at mscss level, see figure 8 for details. 6.14.4.2 pin description the two adc modules in the mscss have the pins described below. the adcx input pins are combined with other functions on t he port pins of the lpc2917/2919/01. the vrefn and vrefp pins are common for both adcs. table 22 shows the adc pins. fig 9. adc block diagram 002aad96 0 adc start 2 adc start 0 apb clock (base_mscss_clk) adc clock (up to 4.5 mhz) (base_adc_clk) apb system bus irq scan irq compare adc2 in[7:0] adc start 1 adc start 3 sync_out adc domain system domain adc control adc registers 3.3 v adc2 3.3 v adc1 analog mux conversion data update configuration data irq adc1 in[7:0] analog mux 3.3 v in 3.3 v in
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 41 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin remark: note that the adc1 and adc2 accept an input voltage up to of 3.6 v (see ta b l e 3 3 ) on the adc1/2 in pins. if the adc is not used, the pins are 5 v tolerant. 6.14.4.3 clock description the adc modules are clocked from two di fferent sources; clk_mscss_adcx_apb and clk_adcx (x = 1 or 2), see section 6.7.2 . note that each adc has its own clk_adcx and clk_mscss_adcx_apb br anch clocks for power management. if an adc is unused both its clk_mscss_adcx_apb and clk_adcx can be switched off. the frequency of all t he clk_mscss_adcx_apb clo cks is identical to clk_mscss_apb since they are derived from the same base clock base_mscss_clk. likewise the fr equency of all the clk_a dcx clocks is identical since they are derived from t he same base clock base_adc_clk. the register inte rface towards the system bus is clocked by clk_ mscss_adcx_apb. control logic for the analog section of the adc is clocked by clk_adcx, see also figure 9 . 6.14.5 pulse width modulator (pwm) the mscss in the lpc2917/2919/01 includ es four pwm modules with the following features. ? six pulse-width modulated output signals ? double edge features (rising and falling edges programmed individually) ? optional interrupt generation on match (each edge) ? different operation modes: continuous or run-once ? 16-bit pwm counter and 16-bit prescale counter allow a large range of pwm periods ? a protective mode (trap) holding the output in a software-controllable state and with optional interrupt generation on a trap event ? three capture registers and capture trigger pins with optional interrupt generation on a capture event ? interrupt generation on match event, capture event, pwm counter overflow or trap event ? a burst mode mixing the external carrier signal with internally generated pwm ? programmable sync-delay output to tr igger other pwm modules (master/slave behavior) table 22. analog to digital converter pins symbol pin name direction description adc1/2 in[7:0] in1/2[7:0] in analog input for 3.3 v adc1/2, channel 7 to channel 0 adcn_ext_start cap1[n] in adc external start-trigger input (n = 1 or 2) vrefn vrefn in adc low reference level vrefp vrefp in adc high reference level
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 42 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.14.5.1 functional description the ability to provide flexible waveforms allows pwm blocks to be used in multiple applications; e.g. dimmer/lam p control and fan control. pu lse-width modula tion is the preferred method for regulating power since no additional heat is generated, and it is energy-efficient when compared with linea r-regulating voltage control networks. the pwm delivers the waveforms/pulses of the desired duty cycles and cycle periods. a very basic application of these pulses ca n be in controlling the amount of power transferred to a load. since the duty cycle of the pulses can be controlled, the desired amount of power can be transferred for a controlled duration. two examples of such applications are: ? dimmer controller: the flexibility of providi ng waves of a desired duty cycle and cycle period allows the pwm to control the amount of power to be transferred to the load. the pwm functions as a dimmer co ntroller in this application ? motor controller: the pwm provides multi- phase outputs, and these outputs can be controlled to have a certain pattern sequence. in this way the force/torque of the motor can be adjusted as desired. this makes the pwm function as a motor drive. the pwm block diagram in figure 10 shows the basic architecture of each pwm. pwm functionality is split into two major parts, a apb domain and a pwm dom ain, both of which run on clocks derived from the base_mscss_cl k. this split into two domains affects behavior from a system-level perspective. the actual pwm and prescale counters are located in the pwm domain but system control takes place in the apb domain. fig 10. pwm block diagram 002aad837 apb system bus irq pwm irq capt_match pwm control & registers update capture data pwm counter value config data irqs pwm, counter, prescale counter & shadow registers match outputs capture inputs trap input carrier inputs sync_in sync_out transfer_enable_in transfer_enable_out apb domain pwm domain
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 43 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin the actual pwm consists of two counters; a 16-bit prescale counter and a 16-bit pwm counter. the position of the rising an d falling edges of the pwm outputs can be programmed individually. the prescale counter allows high system bus frequencies to be scaled down to lower pwm periods. registers are available to capture the pwm counter values on external events. note that in the modulation and sampling subsystem, each pwm has its individual clock source clk_mscss_pwmx (x runs from 0 to 3). both the prescale and the timer counters within each pwm run on this cloc k clk_mscss_pwmx, and all time references are related to the period of this clock. see section 6.15 for information on generation of these clocks. 6.14.5.2 synchronizing the pwm counters a mechanism is included to synchronize the pwm period to other pwms by providing a sync input and a sync output with programmable delay. several pwms can be synchronized using the trans_enable_in/tran s_enable_out and sync_in/sync_out ports. see figure 8 for details of the connections of th e pwm modules within the mscss in the lpc2917/2919/01. pwm 0 can be master over pwm 1; pwm 1 can be master over pwm 2, etc. 6.14.5.3 master and slave mode a pwm module can provide synchronization si gnals to other modules (also called master mode). the signal sync_out is a pulse of one clock cycle generated when the internal pwm counter (re)starts. the signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to pwm shadow register s occurred when the pwm counter restarted. a delay may be inserted between the counter start and generation of trans_enable_out and sync_out. a pwm module can use input signals trans_enable_in and sync_in to synchronize its internal pwm counter and the transfer of shadow registers (slave mode). 6.14.5.4 pin description each of the four pwm modules in the mscss has the following pins. these are combined with other functions on the port pi ns of the lpc2917/2919/01. ta b l e 2 3 shows the pwm0 to pwm3 pins. table 23. pwm pins symbol pin name direction description pwmn cap[0] pcapn[0] in pwm n capture input 0 pwmn cap[1] pcapn[1] in pwm n capture input 1 pwmn cap[2] pcapn[2] in pwm n capture input 2 pwmn mat[0] pmatn[0] out pwm n match output 0 pwmn mat[1] pmatn[1] out pwm n match output 1 pwmn mat[2] pmatn[2] out pwm n match output 2 pwmn mat[3] pmatn[3] out pwm n match output 3 pwmn mat[4] pmatn[4] out pwm n match output 4 pwmn mat[5] pmatn[5] out pwm n match output 5 pwmn trap trapn in pwm n trap input
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 44 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.14.5.5 clock description the pwm modules are clocked by cl k_mscss_pwmx (x = 0 - 3), see section 6.7.2 . note that each pwm has its own clk_ mscss_pwmx branch clock for power management. the frequency of all these clo cks is identical to clk_mscss_apb since they are derived from the same base clock base_mscss_clk. also note that unlike the timer modules in the peripheral subsystem, the actual timer counter registers of the pwm modules run at the same clock as the apb system interface clk_mscss_apb. this clock is in dependent of the ahb system clock. if a pwm module is not used its clk_mscss_ pwmx branch clock ca n be switched off. 6.14.6 timers in the mscss the two timers in the mscss are functionally identical to the timers in the peripheral subsystem, see section 6.12.3 . the features of the timers in the mscss are the same as the timers in the peripheral subsystem, but the capture inputs and match outputs are not available on the device pins. these signals are instead connected to the adc and pwm modules as outlined in the description of the mscss, see section 6.14.1 . see section section 6.12.3 for a functional description of the timers. 6.14.6.1 pin description mscss timer 0 has no external pins. mscss timer 1 has a pause pin available as external pin. the pause pin is combined with other functions on the port pins of the lpc2917/2919/01. ta b l e 2 4 shows the mscss timer 1 external pin. 6.14.6.2 clock description the timer modules in the mscss are clocked by clk_mscss_mtmrx (x = 0 to 1), see section 6.7.2 . note that each timer has its own clk_mscss_mtmrx branch clock for power management. the frequency of all thes e clocks is identica l to clk_mscss_apb since they are derived from t he same base clock base_mscss_clk. note that, unlike the timer modules in the peri pheral subsystem, the actual timer counter registers run at the same clock as the apb system interface clk_mscss_apb. this clock is independent of the ahb system clock. if a timer module is not used its clk_mscss_mtmrx branch clock can be switched off. 6.14.7 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-chan nel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, the user ca n track the position, direction of rotation, and velocity. in addition, a third channel, or index signal, can be used to reset the position counter. the quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over ti me and determine direction of rotation. in addition, the qei can capture the velocity of the encoder wheel. table 24. mscss timer 1 pin symbol direction description mscss pause in pause pin for mscss timer 1
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 45 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin the qei has the following features: ? tracks encoder position. ? increments/ decrements depending on direction. ? programmable for 2x or 4x position counting. ? velocity capture using built-in timer. ? velocity compare function with less than interrupt. ? uses 32-bit registers for position and velocity. ? three position compare registers with interrupts. ? index counter for re volution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with prog rammable delays for encoder input signals. ? can accept decoded signal inputs (clk and direction). ? connected to apb. 6.14.7.1 pin description the qei module in the mscss has the following pins. these are combined with other functions on the port pins of the lpc2917/2919/01. ta b l e 2 5 shows the qei pins. 6.14.7.2 clock description the qei module is clocked by clk_mscss_qei, see section 6.7.2 . the frequency of this clock is identical to clk_mscss_apb si nce they are derived from the same base clock base_mscss_clk. if the qei is not used its clk_mscss_qei branch clock can be switched off. 6.15 power, clock and reset control subsystem the power, clock, and reset control subsystem (pcrss) in the lpc2917/2919/01 includes the clock generator units (cgu0 an d cgu1), a reset ge nerator unit (rgu) and a power management unit (pmu). figure 11 provides an overview of the pcrss. an ahb-to-dtl bridge provides communication with the ahb system bus. table 25. qei pins symbol pin name direction description qei0 idx idx0 in index signal. can be used to reset the position. qei0 pha pha0 in sensor signal. corresponds to pha in quadrature mode and to direction in clock/direction mode. qei0 phb phb0 in sensor signal. corresponds to phb in quadrature mode and to clock signal in clock/direction mode.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 46 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.15.1 clock description the pcrss is clocked by a number of different clocks. cl k_sys_pcrss clocks the ahb side of the ahb to dtl bus bridge an d clk_pcr_slow clocks the cgu, rgu and pmu internal logic, see section 6.7.2 . clk_sys_pcrss is derived from base_sys_clk, which can be switched off in low-power modes. clk_pcr_slow is derived from base_pcr_clk and is always on in order to be able to wake up from low-power modes. fig 11. power, clock, and reset control sub system (pcrss) block diagram 002aae35 5 ahb2dtl bridge reset output delay logic input deglitch/ sync branch clocks grant request wakeup_a ahb_rst scu_rst warm_rst cold_rst pcr_rst rgu_rst por_rst rst (device pin) reset from watchdog counter external oscillator pmu registers clock enable control clock gates low power ring oscillator cgu0/1 registers rgu registers por out0 out1 out5 out7 out9 out6 out11 out pll fdiv[6:0] pll fdiv cgu0 cgu1 pmu rgu ahb master disable:
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 47 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.15.2 clock generation unit (cgu0) the key features are: ? generation of 11 base clocks, selectable from several embedded clock sources. ? crystal oscillator with power-down. ? control pll with power-down. ? very low-power ring oscillator, a lways on to provide a ?safe clock?. ? seven fractional clock dividers with l/d division. ? individual source selector for each ba se clock, with glitch-free switching. ? autonomous clock-activity dete ction on every clock source. ? protection against switching to in valid or inactive clock sources. ? embedded frequency counter. ? register write-protection mechanism to pr event unintentional alteration of clocks. remark: any clock-frequency adjustment has a direct impact on the timing of all on-board peripherals. 6.15.2.1 functional description the clock generation unit provides 11 internal clock sources as described in ta b l e 2 6 . [1] maximum frequency that guarantees stable operation of the lpc2917/2919/01. [2] fixed to low-power oscillator. table 26. cgu0 base clocks number name frequency (mhz) [1] description 0 base_safe_clk 0.4 base sa fe clock (always on) 1 base_sys_clk 125 base system clock 2 base_pcr_clk 0.4 [2] base pcr subsystem clock 3 base_ivnss_clk 125 base ivnss subsystem clock 4 base_mscss_clk 125 base mscss subsystem clock 5 base_uart_clk 125 base uart clock 6 base_iclk0_clk 125 base inte rnal clock 0, for cgu1 7 base_spi_clk 50 base spi clock 8 base_tmr_clk 125 base timers clock 9 base_adc_clk 4.5 base adcs clock 10 reserved - - 11 base_iclk1_clk 125 base inte rnal clock 1, for cgu1
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 48 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin for generation of these base clocks, the cgu consists of primary and secondary clock generators and one output ge nerator for each base clock. there are two primary clock generators: a low-power ring oscillator (lp_osc) and a crystal oscillator. see figure 12 . lp_osc is the source for the base_pcr_clk that clocks the cgu0 itself and for base_safe_clk that clocks a minimum of othe r logic in the device (like the watchdog timer). to prevent the device from losing it s clock source lp_osc cannot be put into power-down. the crystal oscillato r can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected. secondary clock generators are a pll and se ven fractional dividers (fdiv0..6). the pll has three clock outputs: normal, 120 phase-shifted and 240 phase-shifted. fig 12. block diagram of the cgu0 400 khz lp_osc pll fdiv0 external oscillator fdiv1 fdiv6 out 0 out 1 out 11 002aae147 clkout clkout120 clkout240 clock generation unit (cgu0) frequency monitor clock detection ahb to dtl bridge base_sys_clk base_iclk1_clk out 3 base_ivnss_clk out 2 base_pcr_clk base_safe_clk
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 49 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin configuration of the cgu0: for every output generator generating the base clocks a choice can be made from the primary and secondary clock generators according to figure 13 . any output generator (except for base _safe_clk and base_pcr_clk) can be connected to either a fractional divider (fdiv0.. 6) or to one of the outputs of the pll or to lp_osc/crystal osc illator directly. base_safe_clk and base_pcr_clk can use only lp_osc as source. the fractional dividers can be connected to on e of the outputs of the pll or directly to lp_osc/crystal oscillator. the pll is connected to the crystal oscillator. in this way every output generating the base cl ocks can be configured to get the required clock. multiple output generators can be connected to the same primary or secondary clock source, and multiple secondary clock sources can be connected to the same pll output or primary clock source. invalid selections/programming - connecting the pll to an fdiv or to one of the pll outputs itself for example - will be blocked by hardware. the contro l register will not be written, the previous value will be kept, alth ough all other fields will be written with new data. this prevents clocks being blocked by incorrect programming. default clock sources: every secondary clock generator or output generator is connected to lp_osc at reset. in this way the device runs at a low frequency after reset. it is recommended to switch base_sys_clk to a high-frequen cy clock generator as one of the first steps in the boot code after verify ing that the high-frequency clock generator is running. clock activity detection: clocks that are inactive are automatically regarded as invalid, and values of ?clk_sel? that would select th ose clocks are masked and not written to the control registers. this is accomplished by adding a clock detector to every clock fig 13. structure of the clock generation scheme lp_osc pll fdiv0:6 external oscillator 002aad83 4 clkout clkout120 clkout240 output control clock outputs
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 50 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin generator. the rdet register keeps track of which clocks are active and inactive, and the appropriate ?clk_sel? values are masked and unmasked accordingly. each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a chan ge in internal clock status. clock detection is done using a counter running at the base_pcr_clk frequency. if no positive clock edge occurs before the counter has 32 cycles of base_pcr_clk the clock is assumed to be inactive. as base_pcr_clk is slower than any of the clocks to be detected, normally only one base_pcr_clk cyc le is needed to detect activity. after reset all clocks are assumed to be ?non-present?, so t he rdet status register will be correct only after 32 base_pcr_clk cycles. note that this mechanism cannot protect again st a currently-select ed clock going from active to inactive state. ther efore an inactive clock may still be sent to the system under special circumstances, altho ugh an interrupt can still be generated to notify the system. glitch-free switching: provisions are included in th e cgu to allow clocks to be switched glitch-free, both at the output generator stage and also at secondary source generators. in the case of the pll the clock will be stopped and held lo w for long enough to allow the pll to stabilize and lock before being re-enabled. for a ll non-pll generato rs the switch will occur as quickly as possible, although th ere will always be a period when the clock is held low due to synchronization requirements. if the current clock is high and does not go low within 32 cycles of base_pcr_clk it is assumed to be inactive and is asynchronously forced low. this prevents deadlocks on the interface. 6.15.2.2 pll functional description a block diagram of the pll is shown in figure 14 . the input clock is fed directly to the analog section. this block co mpares the phase and frequency of the inputs and generates the main clock 2 . these clocks are either divided by 2 p by the programmable post divider to create the output clock, or sent di rectly to the output. the main output clock is then divided by m by the programmable feedback divider to generate the feedback clock. the output signal of the anal og section is also monitored by the lock detector to signal when the pll has locked onto the input clock. 2. generation of the main clock is restricted by the frequency range of the pll clock input. see table 35 , dynamic characteristics.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 51 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin triple output phases: for applications that require multiple clock phases two additional clock outputs can be enabled by setting register p23en to logic 1, thus giving three clocks with a 120 phase difference. in this mode all three clocks generated by the analog section are sent to the output dividers. when the pll has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown. when the pll lock register is set the second and third phase of the output dividers are syn chronized to the main output clock clkout pll, thus giving three clocks with a 120 phase difference. direct output mode: in normal operating mode (with direct set to logic 0) the cco clock is divided by 2, 4, 8 or 16 depending on the value on the psel[1:0] input, giving an output clock with a 50 % duty cycle. if a hi gher output frequency is needed the cco clock can be sent directly to the output by settin g direct to logic 1. since the cco does not directly generate a 50 % duty cycle clock, th e output clock duty cycle in this mode can deviate from 50 %. power-down control: a power-down mode has been incorporated to reduce power consumption when the pll clock is not needed. this is enabled by setting the pd control register bit. in this mode th e analog section of the pll is tu rned off, the oscillator and the phase-frequency detector are stopped and th e dividers enter a reset state. while in power-down mode the lock output is low, indicating that the pll is not in lock. when power-down mode is terminated by clearing the pd control-register bit the pll resumes normal operation, and makes the lock signal high once it has regained lock on the input clock. 6.15.2.3 pin description the cgu0 module in the lpc2917/2919/01 has the pins listed in ta b l e 2 7 below. fig 14. pll block diagram cco / 2pdiv p23 / mdiv 002aad83 3 bypass direct clkout120 clkout240 clkout clkout input clock psel bits p23en bit msel bits table 27. cgu0 pins symbol direction description xout_osc out oscillator crystal output xin_osc in oscillator crystal input or external clock input
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 52 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.15.3 clock generation for clk_out (cgu1) the cgu1 block is functionally identical to the cgu0 block and generates a dedicated output clock. the cgu1 block uses its own p ll and fractional divider. the plls used in cgu0 and cgu1 are identical (see section 6.15.2.2 ). the clock input to the cgu1 pll is provided by one of two base clocks generated in the cgu0: base_iclk0_clk or base_iclk1_clk. the base clock not used for the pll can be configured to drive the output clock directly. 6.15.3.1 pin description the cgu1 module in the lpc2917/2919/01 has the pins listed in ta b l e 2 7 below. 6.15.4 reset generation unit (rgu) the rgu controls a ll internal resets. the key features of the reset generation unit (rgu) are: ? reset controlled indivi dually per subsystem ? automatic reset stre tching and release ? monitor function to trace resets back to source fig 15. block diagram of the cgu1 pll fdiv0 out 002aae266 clkout clkout120 clkout240 clock generation unit (cgu1) ahb to dtl bridge base_out_clk base_iclk1_clk base_iclk0_clk table 28. cgu1 pins symbol direction description clk_out out clock output
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 53 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? register write-protection mechanis m to prevent unintentional resets 6.15.4.1 functional description each reset output is defined as a combination of reset input sources including the external reset input pins and internal power-on reset, see ta b l e 2 9 . the first five resets listed in this table form a sort of cascade to provide th e multiple levels of im pact that a reset may have. the combined input sources are logically or-ed together so that activating any of the listed reset sources causes the output to go active. 6.15.4.2 pin description the rgu module in the lpc2917/2919/01 has the following pins. table 30 shows the rgu pins. table 29. reset output configuration reset output reset source parts of the device reset when activated por_rst power-on reset module lp_osc; is source for rgu_rst rgu_rst por_rst, rst pin rgu internal; is source for pcr_rst pcr_rst rgu_rst, watchdog pcr internal; is source for cold_rst cold_rst pcr_rst parts with cold_rst as reset source below warm_rst cold_rst parts with warm_rst as reset source below scu_rst cold_rst scu cfid_rst cold_rst cfid fmc_rst cold_rst embedded flash-memory controller (fmc) emc_rst cold_rst embedded sram-memory controller smc_rst cold_rst external static-memory controller (smc) gess_a2a_rst warm_rst gess ahb-to-apb bridge pess_a2a_rst warm_rst pess ahb-to-apb bridge gpio_rst warm_rst all gpio modules uart_rst warm_rst all uart modules tmr_rst warm_rst all timer modules in pess spi_rst warm_rst all spi modules ivnss_a2a_rst warm_rst ivnss ahb-to-apb bridge ivnss_can_rst warm_rst all can modules including acceptance filter ivnss_lin_rst warm_rst all lin modules mscss_a2a_rst warm_rst mscss ahb to apb bridge mscss_pwm_rst warm_rst all pwm modules mscss_adc_rst warm_rst all adc modules mscss_tmr_rst warm_rst all timer modules in mscss i2c_rst warm_rst all i2c modules qei_rst warm_rst quadrature encoder dma_rst warm_rst gpdma controller vic_rst warm_rst vectored in terrupt controller (vic) ahb_rst warm_rst cpu and ahb bus infrastructure
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 54 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.15.5 power management unit (pmu) this module enables software to actively control the system?s power consumption by disabling clocks not required in a particular operating mode. using the base clocks from the cgu as inpu t, the pmu generates branch clocks to the rest of the lpc2917/2919/01. output clocks branched from the same base clock are phase- and frequency-related. these branch clocks can be indivi dually controlled by software programming. the key features are: ? individual clock control for all lpc2917/2919/01 sub-modules ? activates sleeping clocks when a wake-up event is detected ? clocks can be individually disabled by software ? supports ahb master-disable protocol when auto mode is set ? disables wake-up of enabled clocks when power-down mode is set ? activates wake-up of enabled clocks when a wake-up event is received ? status register is available to indicate if an input base clock can be safely switched off (i.e. all branch clocks are disabled) 6.15.5.1 functional description the pmu controls all inte rnal clocks coming out of the cgu0 for power-mode management. with some exceptions, each branch clock can be switched on or off individually under control of software register bits located in its individual configuration register. some branch clocks controlling vital parts of the device oper ate in a fixed mode. ta b l e 3 1 shows which mode- control bits are supported by each branch clock. by programming the configuration register the user can control which clocks are switched on or off, and which clocks are switched off when entering power-down mode. note that the standby-wait-for-interrupt inst ructions of the arm968e-s processor (putting the arm cpu into a low-power state) are not supported. instead putting the arm cpu into power-down should be controlled by disabling the branch clock for the cpu. remark: for any disabled branch clocks to be re-activated their corresponding base clocks must be runnin g (controlled by cgu0). ta b l e 3 1 shows the relation between branch and base clocks, see also section 6.7.1 . every branch clock is related to one particular base clock: it is not possible to switch the source of a branch clock in the pmu. table 30. rgu pins symbol direction description rst in external reset input, active low; pulled up internally
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 55 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin table 31. branch clock overview legend: ?1? indicates that the re lated register bit is ti ed off to logic high, all writes are ignored ?0? indicates that the re lated register bit is ti ed off to logic low, all writes are ignored ?+? indicates that the related register bit is readable and writable branch clock name base clock implemented switch on/off mechanism wake-up auto run clk_safe base_safe_clk 0 0 1 clk_sys_cpu base_sys_clk + + 1 clk_sys base_sys_clk + + 1 clk_sys_pcr base_sys_clk + + 1 clk_sys_fmc base_sys_clk + + + clk_sys_ram0 base_sys_clk + + + clk_sys_ram1 base_sys_clk + + + clk_sys_smc base_sys_clk + + + clk_sys_gess base_sys_clk + + + clk_sys_vic base_sys_clk + + + clk_sys_pess base_sys_clk + + + clk_sys_gpio0 base_sys_clk + + + clk_sys_gpio1 base_sys_clk + + + clk_sys_gpio2 base_sys_clk + + + clk_sys_gpio3 base_sys_clk + + + clk_sys_ivnss_a base_sys_clk + + + clk_sys_mscss_a base_sys_clk + + + clk_sys_dma base_sys_clk + + + clk_pcr_slow base_pcr_clk + + 1 clk_ivnss_apb base_ivnss_clk + + + clk_ivnss_canc0 base_ivnss_clk + + + clk_ivnss_canc1 base_ivnss_clk + + + clk_ivnss_i2c0 base_ivnss_clk + + + clk_ivnss_i2c1 base_ivnss_clk + + + clk_ivnss_lin0 base_ivnss_clk + + + clk_ivnss_lin1 base_ivnss_clk + + + clk_mscss_apb base_mscss_clk + + + clk_mscss_mtmr0 base_mscss_clk + + + clk_mscss_mtmr1 base_mscss_clk + + + clk_mscss_pwm0 base_mscss_clk + + + clk_mscss_pwm1 base_mscss_clk + + + clk_mscss_pwm2 base_mscss_clk + + + clk_mscss_pwm3 base_mscss_clk + + + clk_mscss_adc1_apb base_mscss_clk + + + clk_mscss_adc2_apb base_mscss_clk + + + clk_mscss_qei base_mscss_clk + + +
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 56 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 6.16 vectored interrupt controller (vic) the lpc2917/2919/01 contains a very flexible and powerful vectored interrupt controller to interrupt the arm processor on request. the key features are: ? level-active interrupt request with programmable polarity. ? 56 interrupt-request inputs. ? software-interrupt request capability associated with each request input. ? interrupt request state can be observed before masking. ? software-programmable priority assignments to interrupt requests up to 15 levels. ? software-programmable routing of interr upt requests towards the arm-processor inputs irq and fiq. ? fast identification of interrupt requests through vector. ? support for nesting of interrupt service routines. 6.16.1 functional description the vectored interrupt controller routes incoming interrupt requests to the arm processor. the interrupt target is configured for each interrupt reque st input of the vic. the targets are defined as follows: ? target 0 is arm processor fiq (fast interrupt service). ? target 1 is arm processor irq (standard interrupt service). clk_out_clk bas e_out_clk + + + clk_uart0 base_uart_clk + + + clk_uart1 base_uart_clk + + + clk_spi0 base_spi_clk + + + clk_spi1 base_spi_clk + + + clk_spi2 base_spi_clk + + + clk_tmr0 base_tmr_clk + + + clk_tmr1 base_tmr_clk + + + clk_tmr2 base_tmr_clk + + + clk_tmr3 base_tmr_clk + + + clk_adc1 base_adc_clk + + + clk_adc2 base_adc_clk + + + table 31. branch clock overview ?continued legend: ?1? indicates that the re lated register bit is ti ed off to logic high, all writes are ignored ?0? indicates that the re lated register bit is ti ed off to logic low, all writes are ignored ?+? indicates that the related register bit is readable and writable branch clock name base clock implemented switch on/off mechanism wake-up auto run
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 57 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin interrupt-request masking is performed individu ally per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. the priority levels are defined as follows: ? priority level 0 corresponds to ?masked? (i.e. interrupt requests with priority 0 never lead to an interrupt). ? priority 1 corresponds to the lowest priority. ? priority 15 corresponds to the highest priority. software interrupt support is provided and can be supplied for: ? testing rtos (real-time operating s ystem) interrupt handling without using device-specific interr upt service routines. ? software emulation of an interrupt-requesting device, including interrupts. 6.16.2 clock description the vic is clocked by clk_sys_vic, see section 6.7.2 .
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 58 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 7. limiting values table 32. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit supply pins p tot total power dissipation [1] -1.5 w v dd(core) core supply voltage ? 0.5 +2.0 v v dd(osc_pll) oscillator and pll supply voltage ? 0.5 +2.0 v v dda(adc3v3) 3.3 v adc analog supply voltage ? 0.5 +4.6 v v dd(io) input/output supply voltage ? 0.5 +4.6 v i dd supply current average value per supply pin [2] -98 ma i ss ground current average value per ground pin [2] -98 ma input pins and i/o pins v xin_osc voltage on pin xin_osc ? 0.5 +2.0 v v i(io) i/o input voltage [3] [4] [5] ? 0.5 v dd(io) +3.0 v v i(adc) adc input voltage for adc1/2: i/o port 0 pin 8 to pin 23. [4] [5] ? 0.5 v dda(adc3v3) + 0.5 v v vrefp voltage on pin vrefp ? 0.5 +3.6 v v vrefn voltage on pin vrefn ? 0.5 +3.6 v i i(adc) adc input current average value per input pin [2] -35 ma output pins and i/o pins configured as output i ohs high-level short-circuit output current drive high, output shorted to v ss(io) [6] - ? 33 ma i ols low-level short-circuit output current drive low, output shorted to v dd(io) [6] -+38 ma general t stg storage temperature ? 65 +150 c t amb ambient temperature ? 40 +85 c
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 59 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin [1] based on package heat transfer, not device power consumption. [2] peak current must be limited at 25 times average current. [3] for i/o port 0, the maximu m input voltage is defined by v i(adc) . [4] only when v dd(io) is present. [5] note that pull-up should be off. with pull-up do not exceed 3.6 v. [6] 112 ma per v dd(io) or v ss(io) should not be exceeded. [7] human-body model: discharging a 100 pf capacitor via a 10 k series resistor. esd v esd electrostatic discharge voltage on all pins human body model [7] ? 2000 +2000 v charged device model ? 500 +500 v on corner pins charged device model ? 750 +750 v table 32. limiting values ?continued in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 60 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 8. static characteristics table 33. static characteristics v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; t vj =-40 cto+85 c; all voltages are measured with respect to ground; positive currents flow into the ic; unless otherwise specified. [1] symbol parameter conditions min typ max unit supplies core supply v dd(core) core supply volt age 1.71 1.80 1.89 v i dd(core) core supply current devi ce state after reset; system clock at 125 mhz; t amb = 85 c; executing code while(1){} from flash. -75-ma all clocks off [2] -30475 a i/o supply v dd(io) input/output supply voltage 2.7-3.6v i dd(io) i/o supply current power-down mode - 0.5 3.25 a oscillator supply v dd(osc_pll) oscillator and pll supply voltage 1.71 1.80 1.89 v i dd(osc_pll) oscillator and pll supply current normal mode - - 1 ma power-down mode - - 2 a analog-to-digital converter supply v dda(adc3v3) 3.3 v adc analog supply voltage 3.03.33.6v i dda(adc3v3) 3.3 v adc analog supply current normal mode - - 1.9 ma power-down mode - - 4 a input pins and i/o pins configured as input v i input voltage all port pins and v dd(io) applied; see section 7 [3] [4] ? 0.5 - + 5.5 v port 0 pins 8 to 23 when adc1/2 is used [4] v vrefp all port pins and v dd(io) not applied ? 0.5 - +3.6 v all other i/o pins, rst , trst , tdi, jtagsel, tms, tck ? 0.5 - v dd(io) v v ih high-level input voltage all port pins, rst , trst , tdi, jtagsel, tms, tck; see figure 22 2.0 - - v v il low-level input voltage all port pins, rst , trst , tdi, jtagsel, tms, tck; see figure 21 --0.8v v hys hysteresis voltage 0.4 - - v
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 61 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin [1] all parameters are guaranteed over the virtual junction te mperature range by design. pre-testing is performed at t amb =85 c on wafer level. cased products are tested at t amb =25 c (final testing). both pre-testing and final te sting use correlated test conditions to cover the specified temperature and power-supply voltage range. [2] leakage current is exponential to temperature; worst-case value is at 85 c t vj . all clocks off. analog modules and flash powered down. [3] not 5 v-tolerant when pull-up is on. [4] for i/o port 0, the maximu m input voltage is defined by v i(adc) . [5] for port 0, pin 0 to pin 15 add maximum 1.5 pf for input capa citance to adc. for port 0, pin 16 to pin 31 add maximum 1.0 pf for input capacitance to adc. [6] c xtal is crystal load capacitance and c ext are the two external load capacitors. [7] this parameter is not part of production testing or final te sting, hence only a typical value is stated. maximum and minimum values are based on simulation results. i lih high-level input leakage current --1 a i lil low-level input leakage current --1 a i i(pd) pull-down input current all port pins, v i = 3.3 v; v i = 5.5 v; see figure 23 25 50 100 a i i(pu) pull-up input current all port pins, rst , trst , tdi, jtagsel, tms: v i =0v; v i > 3.6 v is not allowed; see figure 24 ? 25 ? 50 ? 115 a c i input capacitance [5] -38pf output pins and i/o pins configured as output v o output voltage 0 - v dd(io) v v oh high-level output voltage i oh = ? 4ma v dd(io) ?0.4 - - v v ol low-level output voltage i ol =4ma - - 0.4 v c l load capacitance - - 25 pf oscillator v xin_osc voltage on pin xin_osc 0 - 1.8 v r s(xtal) crystal series resistance f osc = 10 mhz to 15 mhz [6] c xtal =10pf; c ext =18pf --160 c xtal =20pf; c ext =39pf --60 f osc = 15 mhz to 20 mhz [6] c xtal =10pf; c ext =18pf --80 c i input capacitance of xin_osc [7] -2pf power-up reset v trip(high) high trip level voltage [8] 1.11.41.6v v trip(low) low trip level voltage [8] 1.01.31.5v v trip(dif) difference between high and low trip level voltage [8] 50 120 180 mv table 33. static characteristics ?continued v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; t vj =-40 cto+85 c; all voltages are measured with respect to ground; positive currents flow into the ic; unless otherwise specified. [1] symbol parameter conditions min typ max unit
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 62 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin [8] the power-up reset has a time filter: v dd(core) must be above v trip(high) for 2 s before reset is de-asserted; v dd(core) must be below v trip(low) for 11 s before internal reset is asserted. [1] conditions: v ss(io) =0v, v dda(adc3v3) =3.3v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 17 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 17 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 17 . [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 17 . [7] the absolute error (e t ) is the maximum difference between the center of the st eps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 17 . [8] see figure 16 . table 34. adc static characteristics v dda(adc3v3) = 3.0 v to 3.6 v; t amb = ? 40 c to +85 c unless otherwise specified; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v vrefn voltage on pin vrefn 0 - v vrefp ? 2v v vrefp voltage on pin vrefp v vrefn +2 - v dda(adc3v3) v z i input impedance between v vrefn and v vrefp 4.4 - - k v ia analog input voltage v vrefn -v vrefp v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] - 1lsb e l(adj) integral non-linearity [1] [4] -- 2lsb e o offset error [1] [5] -- 3lsb e g gain error [1] [6] -- 0.5 % e t absolute error [1] [7] -- 4lsb r vsi voltage source interface resistance [8] --40 k fig 16. suggested adc interface - lpc2917/2919/01 adc1/2 in[y] pin lpc2xxx adc in[y] sample adc in[y] 20 k 3 pf 5 pf r vsi v ss(io), v ss(core) v ext 002aae28 0
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 63 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 17. adc characteristics 002aae703 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out offset error e o gain error e g offset error e o v ia (lsb ideal )
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 64 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 8.1 power consumption conditions: t amb = 25 c; active mode entered executing code from flash; core voltage 1.8 v; all peripherals enabled but not configured to run. fig 18. i dd(core) at different core frequencies (active mode) conditions: t amb = 25 c; active mode entered executing code from flash; all peripherals enabled but not configured to run. fig 19. i dd(core) at different core voltages v dd(core) (active mode) core frequency (mhz) 10 130 90 50 002aae241 40 20 60 80 i dd(core) (ma) 0 core voltage (v) 1.7 1.9 1.8 002aae240 40 20 60 80 i dd(core) (ma) 0 10 mhz 40 mhz 80 mhz 100 mhz 125 mhz
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 65 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin conditions: active mode entered executing code from flash; core voltage 1.8 v; all peripherals enabled but not configured to run. fig 20. i dd(core) at different temperatures (active mode) temperature ( c) ? 40 85 60 10 35 ? 15 002aae239 40 20 60 80 i dd(core) (ma) 0 10 mhz 80 mhz 100 mhz 40 mhz 125 mhz
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 66 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 8.2 electrical pi n characteristics v dd(io) = 3.3 v. fig 21. typical low-level output volt age versus low-level output current v dd(io) = 3.3 v. fig 22. typical high-level output volt age versus high-level output current 002aae689 i ol (ma) 1.0 6.0 4.0 3.0 5.0 2.0 200 400 100 300 500 v ol (mv) 0 85 c 25 c 0 c ? 40 c i oh (ma) 1.0 6.0 4.0 3.0 5.0 2.0 002aae690 2.5 3.0 3.5 v oh (v) 2.0 85 c 25 c 0 c ? 40 c
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 67 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin v i = 3.3 v. fig 23. typical pull-down current versus temperature v i = 0 v. fig 24. typical pull-up current versus temperature 002aae691 temperature ( c) ? 40 85 35 10 60 ? 15 50 70 60 80 i i(pd) ( a) 40 v dd(io) = 3.6 v 3.0 v 2.7 v 002aae692 temperature ( c) ? 40 85 35 10 60 ? 15 ? 80 ? 40 ? 60 ? 20 i i(pu) ( a) ? 100 v dd(io) = 2.7 v 3.3 v 3.6 v
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 68 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 9. dynamic characteristics 9.1 dynamic characteristics: i/o pins, in ternal clock, oscillators, pll, and can table 35. dynamic characteristics v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground; positive currents flow into the ic; unless otherwise specified. [1] symbol parameter conditions min typ max unit i/o pins t thl high to low transition time c l = 30 pf 4 - 13.8 ns t tlh low to high transition time c l = 30 pf 4 - 13.8 ns clkout pin f clk clock frequency on pin clkout - - 40 mhz internal clock f clk(sys) system clock frequency [2] 10 - 125 mhz t clk(sys) system clock period [2] 8 - 100 ns low-power ring oscillator f ref(ro) ro reference frequency 0.36 0.4 0.42 mhz t startup start-up time at maximum frequency [3] -6- s oscillator f i(osc) oscillator input frequency maximum frequency is the clock input of an external clock source applied to the xin_osc pin 10 - 100 mhz t startup start-up time at maximum frequency [3] [4] -500- s pll f i(pll) pll input frequency 10 - 25 mhz f o(pll) pll output frequency 10 - 160 mhz cco; direct mode 156 - 320 mhz t a(clk) clock access time - - 63.4 ns t a(a) address access time - - 60.3 ns
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 69 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin [1] all parameters are guaranteed over the virtual junction te mperature range by design. pre-testing is performed at t amb =85 c ambient temperature on wafer level. cased products are tested at t amb =25 c (final testing). both pre-testi ng and final testing use correlated test conditions to cover the specifi ed temperature and power supply voltage range. [2] see table 26 . [3] this parameter is not part of production testing or final testing, hence only a typical value is stated. [4] oscillator start-up time depends on the quality of the crystal. for most crystals it takes about 1000 clock pulses until the clock is fully stable. jitter specification for can t jit(cc)(p-p) cycle to cycle jitter (peak-to-peak value) on can txdc pin [3] -0.41ns table 35. dynamic characteristics ?continued v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground; positive currents flow into the ic; unless otherwise specified. [1] symbol parameter conditions min typ max unit fig 25. low-power ring oscill ator thermal characteristics temperature ( c) ? 40 85 60 10 35 ? 15 002aae373 500 490 510 520 f ref(ro) (khz) 480 1.9 v 1.8 v 1.7 v
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 70 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 9.2 dynamic characteristics: i 2 c-bus interface [1] all parameters are guaranteed over the virtual junction te mperature range by design. pre-testing is performed at t amb =85 c ambient temperature on wafer level. cased products are tested at t amb =25 c (final testing). both pre-testi ng and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. 9.3 dynamic characteristics: spi [1] all parameters are guaranteed over the virtual junction te mperature range by design. pre-testing is performed at t amb =85 c ambient temperature on wafer level. cased products are tested at t amb =25 c (final testing). both pre-testi ng and final testing use correlated test conditions to cover the specifi ed temperature and power supply voltage range. table 36. dynamic characteristic: i 2 c-bus pins v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground; positive currents flow into the ic; unless otherwise specified [1] symbol parameter conditions min typ [2] max unit t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns table 37. dynamic characteristics of spi pins v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; v dda(adc5v0) = 3.0 v to 5.5 v; t vj =-40 cto+85 c; all voltages are measured with respect to ground; positive currents flow into the ic; unless otherwise specified. [1] symbol parameter conditions min typ max unit f spi spi operating frequency master operation 1 ? 65024 f clk(spi) - 1 ? 2 f clk(spi) mhz slave operation 1 ? 65024 f clk(spi) - 1 ? 4 f clk(spi) mhz t su(spi_miso) spi_miso set-up time t amb = 25 c; measured in spi master mode; see figure 26 -11-ns fig 26. spi data input set-u p time in ssp master mode t su(spi_miso) sckn shifting edges sdon sdin 002aae695 sampling edges
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 71 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 9.4 dynamic characteristics : flash memory and eeprom [1] number of program/erase cycles. table 38. flash characteristics t amb =-40 cto+85 c; v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground. symbol parameter conditions min typ max unit n endu endurance [1] 10000 - - cycles t ret retention time powered 10 - - years unpowered 20 - - years t prog programming time word 0.95 1 1.05 ms t er erase time global 95 100 105 ms sector 95 100 105 ms t init initialization time - - 150 s t wr(pg) page write time 0.95 1 1.05 ms t fl(bist) flash word bist time - 38 70 ns t a(clk) clock access time - - 63.4 ns t a(a) address access time - - 60.3 ns table 39. eeprom characteristics t amb =-40 cto+85 c; v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground. symbol parameter conditions min typ max unit f clk clock frequency 200 375 400 khz n endu endurance 100000 500000 - cycles t ret retention time powered 10 - - years
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 72 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 9.5 dynamic characteristics : external static memory [1] all parameters are guaranteed over the virtual junction te mperature range by design. pre-testing is performed at t amb =85 c ambient temperature on wafer level. cased products are tested at t amb =25 c (final testing). both pre-testi ng and final testing use correlated test conditions to cover the specifi ed temperature and power supply voltage range. [2] when the byte lane select signals are used to c onnect the write enable input (8 bit devices), t cshblsh = ? 0.5 t clcl . [3] when the byte lane select signals are used to c onnect the write enable input (8 bit devices), t cslblsl = t cslwel . [4] for 16 and 32 bit devices. table 40. external static memory interface dynamic characteristics v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground. [1] symbol parameter conditions min typ max unit t clcl clock cycle time 8 - 100 ns t a(r)int internal read access time - - 20.5 ns t a(w)int internal write access time - - 24.9 ns read cycle parameters t cslav cs low to address valid time ? 5 ? 2.5 - ns t oelav oe low to address valid time ? 5 ? wstoen t clcl ? 2.5 ? wstoen t clcl -ns t csloel cs low to oe low time - 0 + wstoen t clcl -ns t su(dq) data input /output set-up time 11 16 22 ns t h(d) data input hold time 0 2.5 5 ns t cshoeh cs high to oe high time - 0 - ns t blslblsh bls low to bls high time - (wst1 ? wstoen +1) t clcl -ns t oeloeh oe low to oe high time - (wst1 ? wstoen +1) t clcl -ns t blslav bls low to address valid time -0 + wstoen t clcl - ns write cycle parameters t cshblsh cs high to bls high time [2] -0 -ns t cslwel cs low to we low time - (wstwen + 0.5) t clcl -ns t cslblsl cs low to bls low time [3] -wstwen t clcl -ns t weldv we low to data valid time - (wstwen + 0.5) t clcl -ns t csldv cs low to data valid time ? 0.5 ? 0.1 0.3 ns t welweh we low to we high time - (wst2 ? wstwen +1) t clcl -ns t blslblsh bls low to bls high time [4] - (wst2 - wstwen +2) t clcl -ns
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 73 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin fig 27. external memory read access cs a d oe/bls t cslav t oelav , t blslav t oeloeh , t blslblsh t csloel t h(d) t su(dq) t cshoeh 002aae68 7 fig 28. external memory write access cs a d we t cslwel t weldv t csldv t welweh t blslblsh 002aae688 t cslblsl bls t csldv t cshblsh
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 74 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 9.6 dynamic characteristics: adc [1] all parameters are guaranteed over the virtual junction te mperature range by design. pre-testing is performed at t amb =85 c ambient temperature on wafer level. cased products are tested at t amb =25 c (final testing). both pre-testi ng and final testing use correlated test conditions to cover the specifi ed temperature and power supply voltage range. [2] duty cycle clock should be as close as possible to 50 %. 10. application information 10.1 operating frequency selection the lpc2917/2919/01 is specified to oper ate at a maximum freq uency of 125 mhz, maximum temperature of 85 c, and maximum core voltage of 1.89 v. figure 29 and figure 30 show that the user can achieve higher operating frequencies for the lpc2917/2919/01 by c ontrolling the temperature and t he core voltage accordingly. table 41. adc dynamic characteristics v dd(core) =v dd(osc_pll) ; v dd(io) = 2.7 v to 3.6 v; v dda(adc3v3) = 3.0 v to 3.6 v; all voltages are measured with respect to ground. [1] symbol parameter conditions min typ max unit f i(adc) adc input frequency [2] 4- 4.5mhz f s(max) maximum sampling rate f i(adc) = 4.5 mhz; f s =f i(adc) /(n + 1) with n=resolution resolution 2 bit - - 1500 ksample/s resolution 10 bit - - 400 ksample/s t conv conversion time in number of adc clock cycles 3 - 11 cycles in number of bits 2 - 10 bits fig 29. core operating frequency versus temperature for different core voltages temperature ( c) 25 85 65 45 002aae194 125 115 135 145 core frequency (mhz) 105 v dd(core) = 1.95 v v dd(core) = 1.8 v v dd(core) = 1.65 v
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 75 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 10.2 spi signal forms fig 30. core operating frequency versus core voltage for different temperatures core voltage (v) 1.65 1.95 1.85 1.75 002aae193 125 115 135 145 core frequency (mhz) 105 25 c 45 c 65 c 85 c fig 31. spi timing in master mode sckn (cpol = 0) sdon sdin 002aae69 3 msb out lsb out data valid sckn (cpol = 1) msb in lsb in data valid sdon sdin msb out lsb out data valid msb in lsb in data valid cpha = 0 cpha = 1
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 76 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin fig 32. spi timing in slave mode sckn (cpol = 0) sdin sdon 002aae69 4 msb in lsb in data valid sckn (cpol = 1) msb out lsb out data valid sdin sdon msb in lsb in data valid msb out lsb out data valid cpha = 0 cpha = 1
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 77 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 10.3 xin_osc input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv rms is needed. for more details see the lpc29xx user manual um10316 . 10.4 xin_osc printed circuit bo ard (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 and c x2 , and c x3 in case of third overtone crystal usage, have a common ground plane. the external components must also be connected to the grou nd plain. loops must be made as small as possible, in order to keep the noise couple d in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. fig 33. slave mode operation of the on-chip oscillator lpc29xx xin_osc c i 100 pf c g 002aae73 0
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 78 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 11. package outline fig 34. package outline sot486-1 (lqfp144) unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.08 0.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 00-03-14 03-02-20 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 1.4 1.1 d 0 5 10 mm scale b p e e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 l qfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 79 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 12. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 12.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 12.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 80 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 12.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 35 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 2 and 43 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 35 . table 42. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 43. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 81 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 35. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 82 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 13. abbreviations 14. references [1] um10316 ? lpc29xx user manual [2] arm ? arm web site [3] arm-ssp ? arm primecell synchronous serial port (pl022) technical reference manual [4] can ? iso 11898-1: 2002 road vehicles - controller area network (can) - part 1: data link layer and physical signalling [5] lin ? lin specification package, revision 2.0 table 44. abbreviations list abbreviation description ahb advanced high-performance bus amba advanced microcontroller bus architecture apb arm peripheral bus bcl buffer control list bdl buffer descriptor list bel buffer entry list bist built-in self test cco current controlled oscillator cisc complex instruction set computers dma direct memory access dsp digital signal processing dtl device transaction level etb embedded trace buffer etm embedded trace macrocell fiq fast interrupt request gpdma general purpose dma irq interrupt request lin local interconnect network mac media access control pll phase-locked loop risc reduced instruction set computer sfsp scu function select port x,y (u se without the p if there are no x,y) scl slot control list uart universal asynchronous receiver transmitter
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 83 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 15. revision history table 45. revision history document id release date data sheet status change notice supersedes lpc2917_19_01_3 20091209 product data sheet - lpc2917_19_01_2 lpc2917_19_01_2 20090617 preliminary data sheet - lpc2917_19_01_1 lpc2917_19_01_1 20090112 preliminary data sheet - -
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 84 of 86 nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
lpc2917_19_01_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 ? 9 december 2009 85 of 86 continued >> nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2.1 general description . . . . . . . . . . . . . . . . . . . . . 5 5.2.2 lqfp144 pin assignment . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . 11 6.1 architectural overview . . . . . . . . . . . . . . . . . . 11 6.2 arm968e-s processor . . . . . . . . . . . . . . . . . . 12 6.3 on-chip flash memory system . . . . . . . . . . . . 13 6.4 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 13 6.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.6 reset, debug, test, and power description . . . 15 6.6.1 reset and power-up behavior . . . . . . . . . . . . 15 6.6.2 reset strategy . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.3 ieee 1149.1 interface pins (jtag boundary-scan test). . . . . . . . . . . . . . . 15 6.6.3.1 etm/etb . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6.4 power supply pins . . . . . . . . . . . . . . . . . . . . . 16 6.7 clocking strategy . . . . . . . . . . . . . . . . . . . . . . 16 6.7.1 clock architecture . . . . . . . . . . . . . . . . . . . . . . 16 6.7.2 base clock and branch clock relationship. . . . 18 6.8 flash memory controller . . . . . . . . . . . . . . . . . 20 6.8.1 functional description. . . . . . . . . . . . . . . . . . . 20 6.8.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8.3 clock description . . . . . . . . . . . . . . . . . . . . . . 21 6.8.4 flash layout . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8.5 flash bridge wait-states . . . . . . . . . . . . . . . . . 22 6.8.6 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.9 external static memory controller . . . . . . . . . . 23 6.9.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.9.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 24 6.9.3 clock description . . . . . . . . . . . . . . . . . . . . . . 24 6.9.4 external memory timing diagrams . . . . . . . . . 24 6.10 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 26 6.10.1 dma support for peripherals. . . . . . . . . . . . . . 26 6.10.2 clock description . . . . . . . . . . . . . . . . . . . . . . 27 6.11 general subsystem. . . . . . . . . . . . . . . . . . . . . 27 6.11.1 general subsystem clock description . . . . . . . 27 6.11.2 chip and feature identification . . . . . . . . . . . . 27 6.11.3 system control unit (scu). . . . . . . . . . . . . . . 27 6.11.4 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.11.4.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 28 6.12 peripheral subsystem . . . . . . . . . . . . . . . . . . 28 6.12.1 peripheral subsystem cloc k description. . . . . 28 6.12.2 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 28 6.12.2.1 functional description . . . . . . . . . . . . . . . . . . 29 6.12.2.2 clock description . . . . . . . . . . . . . . . . . . . . . . 29 6.12.3 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.12.3.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 30 6.12.3.2 clock description . . . . . . . . . . . . . . . . . . . . . . 30 6.12.4 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.12.4.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 31 6.12.4.2 clock description . . . . . . . . . . . . . . . . . . . . . . 31 6.12.5 serial peripheral interface (spi). . . . . . . . . . . 31 6.12.5.1 functional description . . . . . . . . . . . . . . . . . . 32 6.12.5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 32 6.12.5.3 clock description . . . . . . . . . . . . . . . . . . . . . . 33 6.12.6 general-purpose i/o . . . . . . . . . . . . . . . . . . . 33 6.12.6.1 functional description . . . . . . . . . . . . . . . . . . 33 6.12.6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 33 6.12.6.3 clock description . . . . . . . . . . . . . . . . . . . . . . 34 6.13 networking subsystem. . . . . . . . . . . . . . . . . . 34 6.13.1 can gateway . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.13.1.1 global acceptance filter . . . . . . . . . . . . . . . . . 34 6.13.1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 34 6.13.2 lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.13.2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 35 6.13.3 i 2 c-bus serial i/o controllers . . . . . . . . . . . . . 35 6.13.3.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 36 6.14 modulation and sampling control subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.14.1 functional description . . . . . . . . . . . . . . . . . . 36 6.14.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 39 6.14.3 clock description . . . . . . . . . . . . . . . . . . . . . . 39 6.14.4 analog-to-digital converter . . . . . . . . . . . . . . . 39 6.14.4.1 functional description . . . . . . . . . . . . . . . . . . 40 6.14.4.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 40 6.14.4.3 clock description . . . . . . . . . . . . . . . . . . . . . . 41 6.14.5 pulse width modulator (pwm). . . . . . . . . . . . 41 6.14.5.1 functional description . . . . . . . . . . . . . . . . . . 42 6.14.5.2 synchronizing the pwm co unters . . . . . . . . . 43 6.14.5.3 master and slave mode . . . . . . . . . . . . . . . . . 43 6.14.5.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 43 6.14.5.5 clock description . . . . . . . . . . . . . . . . . . . . . . 44 6.14.6 timers in the mscss. . . . . . . . . . . . . . . . . . . 44 6.14.6.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 44 6.14.6.2 clock description . . . . . . . . . . . . . . . . . . . . . . 44 6.14.7 quadrature encoder inte rface (qei) . . . . . . . 44 6.14.7.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 45 6.14.7.2 clock description . . . . . . . . . . . . . . . . . . . . . . 45
nxp semiconductors lpc2917/01; lpc2919/01 arm9 microcontroller with can and lin ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 9 december 2009 document identifier: lpc2917_19_01_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 6.15 power, clock and reset control subsystem . . . 45 6.15.1 clock description . . . . . . . . . . . . . . . . . . . . . . 46 6.15.2 clock generation unit (cgu0) . . . . . . . . . . . . 47 6.15.2.1 functional description. . . . . . . . . . . . . . . . . . . 47 6.15.2.2 pll functional description . . . . . . . . . . . . . . . 50 6.15.2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . 51 6.15.3 clock generation for clk_out (cgu1). . . . . 52 6.15.3.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . 52 6.15.4 reset generation unit (rgu). . . . . . . . . . . . . 52 6.15.4.1 functional description. . . . . . . . . . . . . . . . . . . 53 6.15.4.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 53 6.15.5 power management unit (pmu). . . . . . . . . . . 54 6.15.5.1 functional description. . . . . . . . . . . . . . . . . . . 54 6.16 vectored interrupt controller (vic) . . . . . . . . . 56 6.16.1 functional description. . . . . . . . . . . . . . . . . . . 56 6.16.2 clock description . . . . . . . . . . . . . . . . . . . . . . 57 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 58 8 static characteristics. . . . . . . . . . . . . . . . . . . . 60 8.1 power consumption . . . . . . . . . . . . . . . . . . . . 64 8.2 electrical pin characteristics . . . . . . . . . . . . . . 66 9 dynamic characteristics . . . . . . . . . . . . . . . . . 68 9.1 dynamic characteristics: i/o pins, internal cl ock, oscillators, pll, and can. . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2 dynamic characteristics: i 2 c-bus interface. . . 70 9.3 dynamic characteristics: spi . . . . . . . . . . . . . 70 9.4 dynamic characteristics: flash memory and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.5 dynamic characteristics: external static memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.6 dynamic characteristics: adc . . . . . . . . . . . . 74 10 application information. . . . . . . . . . . . . . . . . . 74 10.1 operating frequency selection . . . . . . . . . . . . 74 10.2 spi signal forms . . . . . . . . . . . . . . . . . . . . . . . 75 10.3 xin_osc input . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4 xin_osc printed circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . 77 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 78 12 soldering of smd packages . . . . . . . . . . . . . . 79 12.1 introduction to soldering . . . . . . . . . . . . . . . . . 79 12.2 wave and reflow soldering . . . . . . . . . . . . . . . 79 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 79 12.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 80 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 83 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 84 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 84 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 84 17 contact information . . . . . . . . . . . . . . . . . . . . 84 18 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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